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12436 Discussions

Cyclone IV : boot nios from epcs

Honored Contributor II

Dear all, 


I'm trying to run the nios directly from the flash (epcs16) on startup, but even if I apply step by step instructions on different files given by Altera, I never succeeded (the fpga works).  

- Generic Nios II Booting Methods User Guide 

- Enabling Nios® II Boot from Quad Serial Configuration(EPCQ) and Serial Configuration (EPCS) devices inQuartus® II 13.0 

- Nios II Processor Booting From Altera Serial Flash (AN736) 


Could you help me please? 


Here is what I do 


hardware configuration:  


A: Nios II (e) and Reset vector on epcq_controller memory 

B: on chip ram 

C: active serial flash controller (epcs 16)  

(there are different flash controller: legacy...) 


D: Clock bridge to get a 25MHz because of epcs clock constraint  


software configuration: 


1. Build Project 

2. Open Nios II command shell: 


sof2flash --input=hw.sof --output=hw.flash –epcs –verbose 

elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose 

nios2-elf-objcopy --input-target srec --output-target ihex sw.flash sw.hex 


output generation:  


SOF file with SOF Data (no compression) 

And Hex data 


  • Big endian 

  • Relative address 




Thank you, 

0 Kudos
4 Replies
Honored Contributor II

I tried again but it doesn't work. 

Any idea? 


Thank you!
Honored Contributor II

For the software configuration, can you try the mem_init_generate tool instead of sof2flash or elf2flash tool? 

Any more description when you say it never works? 

If you programmed a JIC file containing only SOF, does the FPGA configuration works?
Honored Contributor II



Thanks for you answer. 

When I programmed the FPGA with a .pof or .jic file containing only the SOF, the FPGA configuration worked. Then, I added the nios code to the POF and the FPGA also worked. 


I'm going to try with the mem_ini_generate, and I'll set the generated hex file to the absolute address + 1 after the FPGA bitstream. 


Thank you
Honored Contributor II

Take note on the reset vector offset as well, make sure it does not overlap the configuration bitstream.