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Hi,
I have a built a system using Qsys and loaded the compiled system into the FPGA. On the software side, I'm able to run the example hello world program on the DS-5. I built an application, used arm-altera-eabi-gcc compiler and used the cycloneV-dk-ram-hosted.ld linker script to build the program. I have attached the console log. I'm not sure of what files generated by qsys is to be included for building the program since the application needs to know about the ip's used in the system. Could anyone please advise me on this issue? I'm using a Cyclone V Arrow SoCkit with Quartus 14.1 and DS-5 Altera edition. Thanks in advance. Best Regards, Nitin.Link Copied
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I tried running the Altera example project of altera-socfpga-hardwarelib-fpga-cv-gnu. This same issue repeats for the example project as well. The console messages are as shown:
Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost source /v "D:\Altera\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py" No SYSID registers could be found. Has a peripheral description file been supplied? cd "C:\Users\Administrator\Documents\DS-5 Workspace\Altera-SoCFPGA-HardwareLib-Timer-CV-GNU" Working directory "C:\Users\Administrator\Documents\DS-5 Workspace\Altera-SoCFPGA-HardwareLib-Timer-CV-GNU" source /v "C:\Users\Administrator\Documents\DS-5 Workspace\Altera-SoCFPGA-HardwareLib-Timer-CV-GNU\debug-hosted.ds" +reset system Execution stopped due to a breakpoint or watchpoint: S:0x00000000 S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8 +wait 30s +stop WARNING(CMD315): Target is not running +wait 30s +set semihosting enabled false +loadfile "$sdir/u-boot-spl.axf" 0x0 Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF6AA3 (size 0x6AA4) Loaded section .rodata: S:0xFFFF6AA4 ~ S:0xFFFF866D (size 0x1BCA) Loaded section .data: S:0xFFFF8670 ~ S:0xFFFF9543 (size 0xED4) Entry point S:0xFFFF0000 Target has been reset Execution stopped due to a breakpoint or watchpoint: S:0x00000000 S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8 +set semihosting enabled true Semihosting server socket created at port 8000 +delete All user breakpoints deleted +tbreak spl_boot_device Breakpoint 1 at S:0xFFFF13B8 on file spl.c, line 71 on file spl.c, line 81 +run Reloading program Starting target with image C:\Users\Administrator\Documents\DS-5 Workspace\Altera-SoCFPGA-HardwareLib-Timer-CV-GNU\u-boot-spl.axf Running from entry point +wait The program would get stuck after this wait statement. Please advise if I have missed anything. Thanks and Regards, Nitin.- Mark as New
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Could you load the golden example from rocket board first, at least we able to isolate if your own qsys design is causing some trouble.
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