Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12366 Discussions

Cyclone V GT : Avalon data width and frequency ?

Yogesh
Novice
191 Views

If I am using cyclone V GT fpga , can I expect to get 128bits data per clock cycle from avalon interface​ at 200 MHz?

If not what is the max data width and frequency of memory controller(avalon ) a good code can achieve ?​

0 Kudos
1 Reply
NurAida_A_Intel
Employee
123 Views

Hi Sir,

 

 

The width of data bus on the Avalon-MM interface is depend on the particular protocol's data width.

 

Full rate results in a width of 2× the memory data width. Half rate results in a width of 4× the memory data width. Quarter rate results in a width of 8× the memory data width. To determine the Avalon-MM interface rate selection for the memory, refer to the local interface clock rate for your target device in the External Memory Interface Spec Estimator here --> https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/exter...

 

Thanks

 

BR,

Aida

Reply