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Altera_Forum
Honored Contributor I
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Cyclone V SOC ARM DMA

Hello, 

 

Does the Cortex ARM A9 processor of the Cyclone V SOC FPGA have a hard silicone DMA ? 

If so, can this DMA be configured to access data from the FPGA through the H2F 128 bit bridge ?
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Altera_Forum
Honored Contributor I
132 Views

Hi, referring to the Technical Reference DOcument here: 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v4.pdf 

 

The Cyclone V SOC has an (hardened) DMA-330 instance that connects to the L3 interconnect switch via 64-bit bus. So yes, technically it can be used to access data in the FPGA using H2F bridge, but it will not be efficient since the bandwidth of the bridge is much larger.
Altera_Forum
Honored Contributor I
132 Views

You mean it would be inefficient because the DMA is only 64 bits while the bus is 128 ?

Altera_Forum
Honored Contributor I
132 Views

It is not efficient if you are depending on it to move large volume of critical data (needed for the system processing, for example). Also looking at the example here: 

https://rocketboards.org/foswiki/view/projects/datamover 

 

The H2F bridge is running at 128-bit width to the FPGA at 133.33MHz (~2.1GB/s of bandwidth) vs the DMA which is running at 64-bit width to the L3 Interconnect at L4 clock of 100MHz (~0.8GB/s). 

 

If I am not mistaken the DMA is still useful to perform task such as moving the FPGA rbf image for programming the logic (where you boot HPS first, then program FPGA). Just probably not for bandwidth-starved applications :)
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