Hello,In my Cyclone V SOC device I have an F2S bridge implemented to facilitate memory sharing between the FPGA and HPS. The base address I'm using is 0x30000000. The FPGA writes images to a cyclic frame buffer (of 8 frames) that starts at the above address. Most of the time the HPS reads good images from the frame buffer but sometimes it reads an image that's completely dark ( all zero ). My question - how is the arbitration of the F2S bridge being taken care of ? What if the HPS tries to access a memory location that's currently being written by the FPGA ?
--- Quote Start --- Did you ever get anywhere with this. I am having a terrible time getting consistency with bridges and bigger sets of data. THANKS --- Quote End --- Yes - but it turned out to be a software bug. What problem are you facing ?
Got an IP that writes the data to a big buffer (currently we are using a ramp to validate the data movement) and the data is not consistent.My device driver tells the IP we want data and the IP freezes the buffer and interrupts the driver. When I do the copy_to_user and check the data there are inconsistencies. I check the data in the device driver and it shows the same problem (ruled out the 'copy_to_user'). Some evaluation boards it works fine others it doesn't. Really hard to think our custom board is going to be successful when we can't get consistencies with eval boards and the same code and device driver that is so simple.
Sounds like issues with the U-BOOT's configuration of the F2S bridge...Most reference designs I've seen have the BSP configured to work with the F2H bridge (not the F2S). We invested a lot of effort to make it work with the F2S.
So you are saying that in order to get this working reliably I need to work on the u-boot and that is what you invested the effort in to make your F2S work properly?