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Altera_Forum
Honored Contributor I
1,625 Views

Cyclone V SoC, DE1-SoC Board. Ethernet and USB don't work with custom kernel

Hi, 

 

I'm trying to build a custom Linux system on a DE1-SoC board by Terasic. The stock Linux works fine. Even with my own preloader and U-boot. 

 

Currently I'm trying to build a custom Kernel. I need Kernel Version 4.5.2. I compiled the Kernel using socfpga_defconfig. 

In addition to that I searched for a device tree for the DE1 SoC Board. 

 

the Kernel is running and the SD card is working. However, USB and Ethernet aren't working. 

I attached my Device-Tree-File. It includes the "standard" include files that come with the linux kernel. 

 

the first Problem I have is the one with the Ethernet. 

I added a custom mdio section to the gmac1 device because without it Linux couldn't detect the PHY. 

My Ethernet config looks like that: 

 

&gmac1 { status = "okay"; phy-mode = "rgmii"; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; txc-skew-ps = <2600>; rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; /* CUSTOM Adaptations */ interrupt-parent = < &intc >; address-bits = < 48 >; micrel-ksz9021rlrn-clk-skew = < 0xA0E0 >; micrel-ksz9021rlrn-rx-skew = < 0x0 >; max-frame-size = <3800>; /* Custom MDIO Block. Seems to work. stmmac now checks address of PHY */ mdio0 { # address-cells = <1>; # size-cells = <0>; compatible = "snps,dwmac-mdio"; phy1: ethernet-phy@0 { /* No options here */ }; }; };  

 

Now the problem: 

Inside of Linux everything seems fine. I have a eth0 Network device that automatically detects link etc. when I plug in the LAN cable dmesg shows 

socfpga-dwmac ff702000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx  

I can assign a IP address to the interface as well. Even the MAC address configured in u-boot is set up correctly. 

Despite all that, the interface isn't working at all. 

I connected the DE1 SoC directly to an other PC. As soon as I start ping on the DE1 SoC the LEDs of the PC indicate that Ehternet traffic is present. But I can't view any data via Wireshark. I don't get it. It's like the Ethernet is sending with the wrong frequency. I just don't get it. 

 

 

My second problem is the USB interface. As you can see in my dts-File, I'm just activating the module and leave everything as it is defined in the standard includes supplied with the kernel. I get following output when the board boots: 

usb 1-1: new high-speed USB device number 2 using dwc2 random: init urandom read with 9 bits of entropy available hub 1-1:1.0: USB hub found hub 1-1:1.0: 2 ports detected 

For me this seems correct. However, no USB device is detected when I connect it to the board. dmesg doesn't show anything. 

If I boot with a connected USB-Device (USB Memory Stick) and unplug it. I get following dmesg message: 

usb 1-1.2: USB disconnect, device number 3 

I'm also not able to identify the problem here. 

 

I hope you can help me to get this thing working. 

 

Thanks! 

 

 

EDIT: I tried the 4.1-ltsi kernel version from the Altera Open Source Repo https://github.com/altera-opensource/linux-socfpga/tree/socfpga-4.1-ltsi. This Kernel works.  

 

Why does the mainline kernel not work although the Cyclone V SoC is supported?
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2 Replies
Altera_Forum
Honored Contributor I
130 Views

I tried to work with 10/100Mbs ethernet interface in the DE1-SoC board. After a while, I found that the KSZ9021RN PHY chip (the PHY chip used in the DE1-SoC board connected to the HPS of the Cyclone V) has two alternatives to manage the speed: (1) the MII interface for 10/100Mbps and (2) GMIII for 1Gbps. Both alternatives have specific pins in the PHY chip that have to connected to the Cyclone V. For instance, one of these pins is the transmit clock: (1) TX_CLK for MII interface and it is an input for the MAC and (2) GTX_CLK for GMII interface and it is an output for the MAC. 

From the datasheet of the PHY I cannot find a way to manage the ethernet speed according the GTX_CLK. The ethernet speed is changed changing the interface from MII to GMIII. This is not the way that the standard defines the GMII interface. 

Unfortunatelly, in the DE1-SoC board, only the GTX_CLK signal is connected and consequently I cannot know how the PHY chip can be used in 10/100Mbps. 

Conclusion: the DE1-SoC does not support 10/100Mbps or I am missing some information from the board schematics.
Altera_Forum
Honored Contributor I
130 Views

 

--- Quote Start ---  

I tried to work with 10/100Mbs ethernet interface in the DE1-SoC board. After a while, I found that the KSZ9021RN PHY chip (the PHY chip used in the DE1-SoC board connected to the HPS of the Cyclone V) has two alternatives to manage the speed: (1) the MII interface for 10/100Mbps and (2) GMIII for 1Gbps. Both alternatives have specific pins in the PHY chip that have to connected to the Cyclone V. For instance, one of these pins is the transmit clock: (1) TX_CLK for MII interface and it is an input for the MAC and (2) GTX_CLK for GMII interface and it is an output for the MAC. 

From the datasheet of the PHY I cannot find a way to manage the ethernet speed according the GTX_CLK. The ethernet speed is changed changing the interface from MII to GMIII. This is not the way that the standard defines the GMII interface. 

Unfortunatelly, in the DE1-SoC board, only the GTX_CLK signal is connected and consequently I cannot know how the PHY chip can be used in 10/100Mbps. 

Conclusion: the DE1-SoC does not support 10/100Mbps or I am missing some information from the board schematics. 

--- Quote End ---  

 

 

Yes, I believe you are right. I also remembered reading that Cyclone V SoC does not support RMII PHY through the HPS Pins (RMII is only supported if exported to the FPGA fabric) in the erratum before.
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