Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12435 Discussions

Cyclone V, sharing memory between FPGA and HPS

Honored Contributor II

Hello. I'm using de0-nano-SoC and want FPGA and HPS to have access to the same memory. I use GHRD as base project. In Qsys I have activated "enable in-system memory content editor" to see how it works. When system is started I can see two Instances, and it's strange, because I have only one on_chipmemory2_0 in Qsys. 

In the following code in Verilog I write some bytes to RAM: 

soc_system_onchip_memory2_0 m(.address(0) , .byteenable(4'b1111) , .chipselect(1) , .clk(FPGA_CLK1_50) , .clken(1'b1) , .reset(hps_fpga_reset_n) , .reset_req(1'b0) , .write(1'b1) , .writedata(32'hF0F0F0F0) , .readdata(datain) ); 

As result I can see these bytes in in-system memory editor : but I can find it only in the second Instance (see screenshot) 


On my C part I use the following code to get base address: 

#define HW_REGS_BASE ( ALT_STM_OFST )#define HW_REGS_SPAN ( 0x04000000 )# define HW_REGS_MASK ( HW_REGS_SPAN - 1 )# define ALT_AXI_FPGASLVS_OFST (0xC0000000) // axi_master virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, ALT_AXI_FPGASLVS_OFST );  


Then, when I use C app to change memory on this base address I can see these changes in in-system memory editor: 


So, I can't interact between FPGA and HPS because FPGA uses "second" instance and HPS uses "first" instance of "on_chipmemory2_0"(??). 


Can you please explain why I have two Instances on in-system memory editor and how I can get "first" instance form FPGA, or "second" instance from HPS to be able share data between them. 


Many thanks! I'm golang developer and new in FPGA, will appreciate if you help!
0 Kudos
3 Replies
Honored Contributor II

I see... There is one instance in soc_system.v file. This way I see two instances in in-system memory editor.  


Is it correct way if I write code inside soc_system.v to use this instance? Or here is another way how I can interact with this RAM on FPGA side?
Honored Contributor II

The instance in soc_system.v doesn't write data to RAM. So Iv' try to delete it from there and write own instance in main file. I can see this instance in in in-system memory editor and bytes I wrote, but now I can't see it from HPS. It makes me sick :)  

I can't find any tutorial how I can implement it...
Honored Contributor II

Is there any way to read data on FPGA side which was written by HPS (trough h2f axi port)?