I have a design for CycloneV SoC (DE0 Nano SoC board) that includes a NIOS2/e, transferring data to the HPS' DDR3 memory over the f2h_sdram interface, via an adress span expander, using an mSGDMA component.
The mSGDMA is configured with 4kB max transfer size.
Everything is working fine when I set the mSGDMA transfer size anywhere between 0 and 2047 bytes, but when I try with any size above (and including) 2048 bytes, even though the altera msgdma functions still return "success", the transfer does not happen (I check memory on the HPS side, and see that memory was not modified).
I am puzzled as to what could be causing this effect ?
I went a little further: if I go through the f2h_axi_slave bridge of the HPS instead of the f2h_sdram, the DMA transfer works correctly at 2048 bytes (and above, up to 4096 bytes which is the limit I set).
Any idea why using the (faster) f2h_sdram would specifically fail above 2047 bytes / what setting in the f2h_sdram I might have missed ?