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Altera_Forum
Honored Contributor I
1,289 Views

DDR Critical Warning

Hello everybody,  

 

I am working with a cyclone III FPGA, when I add in my sopc system the ddr controller with the clock bridge all of the bottom messages appear. My system works up to 96 MHz and the ddr controller with 110MHz. 

 

Anyone can give me some advice to fix them? 

 

Many thanks. 

 

ifdm 

 

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

 

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

 

Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions 

 

Critical Warning: Timing requirements not met 

 

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[1], when fed by another PLL, must have bandwidth mode set to High instead of Medium 

 

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[2], when fed by another PLL, must have bandwidth mode set to High instead of Medium
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3 Replies
Altera_Forum
Honored Contributor I
94 Views

Hi again, 

 

I suppouse there is no easy answer for these critical warnings. 

 

For trying to guest a solution I suggest to explain each error.  

If someone can contribute I 'll be grateful. 

 

The first one: 

"the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL" 

 

When I attach the ddr controller into the sopc system, the clock wich feeds the component is the external clk connected to niosII. In my design this clock comes from another PLL. I have read that in cycloneIII there are no neighboring PLLs, is that true?  

 

 

The second one: 

"must have bandwidth mode set to High instead of Medium" 

The ddr controller pll has auto mode in the bandwith option. I suppouse when I work with devices which have a speed grade of 8, it is no possible for the system to implement high bandwith, am I right?  

 

The third one: 

"Timing requirements not met" 

When I use the timing analyzer, the top failing paths belong to the clock crossing bridge, has something to do with the two errors commented above? 

 

The fourth one: 

"Read Capture and Write timing analyses may not be valid" 

No idea from where start. 

 

Many thanks! 

 

ifdm
Altera_Forum
Honored Contributor I
94 Views

The solution has been connecting the ddr controller clk to the general clock of the system instead of chaining two pll's, now both of them, the pll of the general system and the pll of the ddr controller are fed by the same clock.

Altera_Forum
Honored Contributor I
94 Views

Have you solved all the Critical warnings? We run into similar warnings. 

 

Thank you very much! 

 

 

 

--- Quote Start ---  

Hello everybody,  

 

I am working with a cyclone III FPGA, when I add in my sopc system the ddr controller with the clock bridge all of the bottom messages appear. My system works up to 96 MHz and the ddr controller with 110MHz. 

 

Anyone can give me some advice to fix them? 

 

Many thanks. 

 

ifdm 

 

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

 

Critical Warning: PLL clock nios32|the_altmemddr_0|altmemddr_0_controller_phy_inst|altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

 

Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions 

 

Critical Warning: Timing requirements not met 

 

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[1], when fed by another PLL, must have bandwidth mode set to High instead of Medium 

 

Critical Warning: ALTMEMPHY PLL, nios32:nios32|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_rnk3:auto_generated|clk[2], when fed by another PLL, must have bandwidth mode set to High instead of Medium 

--- Quote End ---  

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