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DDR SDRAM won't fit!

Altera_Forum
Honored Contributor II
1,319 Views

Hi All, 

I am using a cyclone III starter kit, which has the EP3C25F324C6 FPGA on and the zentel A3S56D40ETP-G5 SD-RAM. 

 

I have (i think) added the DDR ram controller in QSYS correctly (I used the information in the system architect design tutorial, which I appreciate s for the NEEK). 

 

I then generated the system and all is OK, no warnings and no errors. I then dropped this into a quartus schematic, connected all the IO to the outputs and bidirectionals. I then did analysis and elaboration which went OK but when I try to compile the project i get some nasty erros the chief of which are: 

 

Error (171000): Can't fit design in device. 

 

I find this hard to believe as there is nothing else in the system to speak of! 

 

also I get: 

 

Error (165024): The DQ group with DQS pin "MEMDQS[1]" has invalid DQ group assignements. 

 

Error (165024): The DQ group with DQS pin "MEMDQS[0]" has invalid DQ group assignements. 

 

I am a little puzzled to say the least. 

 

If someone could shed some light on this for me I would be most grateful. 

D
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7 Replies
Altera_Forum
Honored Contributor II
154 Views

When You generate DDR controller, the core also generates a TCL script. Run it.

Altera_Forum
Honored Contributor II
154 Views

Hi Socrates, 

 

There seem to be quite a lot of TCL scripts generated that are related to the SDRAM, some are in the synthesis/submodules folder and some are in the project folder. Which are you referring to? and what do you mean by run it! 

 

thanks for taking the time to help. 

D
Altera_Forum
Honored Contributor II
154 Views

In Quartus: Tools -> TCL Scripts.

Altera_Forum
Honored Contributor II
154 Views

Woohoo, it's alive! 

 

It appears I had two instances of the ALTMEMPHY trying to fit into the FPGA, quite how that happened I don't know but it became apparent when I looked at the TCL file you suggested and saw two lots of differently named tcl scripts. So I rebuilt everything and tried again and it worked. I know have a simple program running from the SDRAM so thank you SOcrates. 

D
Altera_Forum
Honored Contributor II
154 Views

Hi All, 

I am using a cyclone III starter kit, which has the EP3C25F324C6 FPGA on and the zentel A3S56D40ETP-G5 SD-RAM. 

 

I have (i think) added the DDR ram controller in QSYS correctly (I used the information in the system architect design tutorial, which I appreciate s for the NEEK). 

 

I then generated the system and all is OK, no warnings and no errors. I then dropped this into a quartus schematic, connected all the IO to the outputs and bidirectionals. I then did analysis and elaboration which went OK but when I try to compile the project i get some nasty erros the chief of which are: 

 

Error (171000): Can't fit design in device. 

 

I find this hard to believe as there is nothing else in the system to speak of! 

 

also I get: 

 

Error (165024): The DQ group with DQS pin "MEMDQS[1]" has invalid DQ group assignements. 

 

Error (165024): The DQ group with DQS pin "MEMDQS[0]" has invalid DQ group assignements. 

 

I am a little puzzled to say the least. 

 

If someone could shed some light on this for me I would be most grateful. 

D
Altera_Forum
Honored Contributor II
154 Views

 

--- Quote Start ---  

When You generate DDR controller, the core also generates a TCL script. Run it. 

--- Quote End ---  

 

 

Hi Socrates,  

I have an issue with fitting DDR SDRAM controller on Cyclone III (3C120). I am building a triple-speed Ethernet module using Qsys as per the altera example http://www.altera.com/support/examples/nios2/exm-tse-sgdma.html?gsa_pos=1&wt.oss_r=1&wt.oss=triple 

speed ethernet 13.1  

 

When I try to build my project in Quartus II, I see the following errors: 

Error (165011): altmemphy pin placement was unsuccessful 

Error (165024): The DQ group with DQS pin "mem_dqs_to_and_from_the_ddr2_bot[0]" has invalid DQ group assignments 

.. 

Error (171000): Can't fit design in device 

 

Prior to compiling my design, I had run the TCL script, generated by the Qsys. But still, the fitting error persists.  

And, I do not see multiple instance of any design component in my top module. Also, I've a query regarding any modification that is required  

to the TCL script, before I run it? 

 

Thank you very much.
Altera_Forum
Honored Contributor II
154 Views

I was able to fix this issue by modifying the pin assignments. (ex: mem_dqs_to_and_from_the_ddr2_bot[0] set to SSTL-18 class I (as suggested in the flow messages )) and by back annotating the pin assignments made during the compilation phase.

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