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Altera_Forum
Honored Contributor I
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DDR memory access problem

Hi all, 

 

I am a new guy to NIOS world, recently I am working on a project to catch 100MHz ADC data and store it in DDR memory, I use SOPC to build NIOS-II CPU and related slaves such as system_id, epcs, on-chip ram, and of course DDR controller with altmemphy. and I wrote a custom IP basically is a DMA with only write master, and receive data from external and save it to a dcfifo, data input rate=100MHz and write master running on 150MHz, for DDR controller I choose preset of MT46V16M16-5B(256Mb) from Micron, mine is MT46V32M16-5B(512Mb) so modified column address width to 10b, and leave rest of the parameters untouched. I read the parameters for auto-refresh period is 7us. I try to verified my design using a 0~4096 ramp counter inside FPGA instead of a real external ADC data input, and verified it both on DDR and on-chip ram, it works fine on on-chip ram but having some problem on DDR, please see the attached Excel file. In the Excel file, at DDR column, data looks ok at the beginning but start getting repeated data around# 342 to# 665 with address increased but data rate gets slower, after# 665 data rate looks correct but still repeated data and updated every 3 data a time like 111444777..., could some body give me some idea of what might be wrong with the design or something I can do to figure it out, every opinion is appreciated, thanks. I haven't tried to run system speed at 166MHz or higher, I think I should try it and I will update my results later.  

 

 

Regards, 

Wade
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