DDR problem, the mem_clk_n signal doesn't generate
I have a problem when I use ddr interface. The ddr chip is Micron MT 16M16BG-6:F, the fpga chip is ep3c120. When I build a sopc, and run the nios program in the ddr, the consle shows that: Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x200CDC7 Leaving target processor paused The address of 0x20000000 is the start address of ddr sdram, so I think that there is some problem in the ddr interface. Therefore I use the singaltap to capture the signal of ddr interface, I find that the mem_clk_n singal doesn't generate, however the mem_clk has generated. The mem_clk_n and the mem_clk are assigned to a pair of DIFFIO pins. The signaltap wave is in the following picture. Thanks for your help!