I have a Qsys system with a DDR3 UNIPHY controller instantiated and it works. I can read and write from Nios and I can use a DMA engine to pull data and stream it over the ethernet.But I am having trouble creating a master to drive the DDR3 controller. I want to be able to buffer up data in the DDR3 using my own logic block with a MM master port. I have the block created and have it connected in my QSYS system but am never able to get the waitrequest signal to show up in my block from the DDR3 controller. I have a signal tap and can see the "avl_ready" signal coming from the ddr3 controller but it does not appear to be connected to my blocks' wait request signal. Does anyone have an example MM master that drives a DDR3 controller?
I got it working by moving my DDR3 controller to base address 0x00000000 in the system. The avalon writedata port on the DDR3 controller is 128bits wide so when I increment my address on the custom master, I increment by 0x10 (16 bytes or 128bits) at a time and everything is working nicely. This gets translated by the fabric and I can see the lower 4 bits of my master write address port are removed and the DDR3 controller is writing in 128bit chunks.The question is how to get a non zero base address to work? If my DDR3 controller is at base address 0x10000000 and spans 0x1FFFFFFF; What address should I put out on my custom masters' write address port? I was trying to use 0x1XXXXXXX without luck. What am I doing wrong? I assumed everything that you did over the avalon interface was byte addressable, is this not the case?
--- Quote Start --- Address is 32bit wide,but addr is a cache flag.so there is just 2G byte in avalon bus that you can access. when addr is 1,it means no cache access. --- Quote End --- I do know about the cache bypass. My memory only uses 29 bits (0x1FFFFFFF) of byte addressable memory space. I'm not asserting bit 31 or trying to use it. that would be 0x8XXXXXX