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DDR3 on Cyclone V E

Altera_Forum
Honored Contributor I
1,112 Views

Hi  

 

I would like to connect the MT41J128M16JT-125 with the uniPHY to my Cyclone V E as a hard memory interface. 

 

My clk_0 is 50MHz and the Systemclock is 80MHz. I connected the cmd and fifos from the ddr3 to the 80MHz, was this correct? 

 

The problem is, I get the following errors: 

 

Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value of '500 ps' on node 'QSYS_46C:inst2|QSYS_46C_ddr3_control:ddr3_control|QSYS_46C_ddr3_control_pll0:pll0|pll6~PLL_OUTPUT_COUNTER'. 

Info: "0 ps" is a legal value 

Info: "417 ps" is a legal value 

Info: "833 ps" is a legal value 

Info: "1250 ps" is a legal value 

Info: "1667 ps" is a legal value 

Info: "2083 ps" is a legal value 

Info: "2500 ps" is a legal value 

Info: "2917 ps" is a legal value 

Info: "3333 ps" is a legal value 

Info: "3750 ps" is a legal value 

Info: "4167 ps" is a legal value 

Info: "4583 ps" is a legal value 

Info: "5000 ps" is a legal value 

Info: "5417 ps" is a legal value 

Info: "5833 ps" is a legal value 

Info: "6250 ps" is a legal value 

Info: "6667 ps" is a legal value 

Info: "7083 ps" is a legal value 

Info: "7500 ps" is a legal value 

Info: "7917 ps" is a legal value 

Info: "8333 ps" is a legal value 

Info: "8750 ps" is a legal value 

Info: "9167 ps" is a legal value 

Info: "9583 ps" is a legal value 

Info: "10000 ps" is a legal value 

Info: "10417 ps" is a legal value 

Info: "10833 ps" is a legal value 

Info: "11250 ps" is a legal value 

Info: "11667 ps" is a legal value 

Info: "12083 ps" is a legal value 

Info: "12500 ps" is a legal value 

Info: "12917 ps" is a legal value 

Info: "13333 ps" is a legal value 

Info: "13750 ps" is a legal value 

Info: "14167 ps" is a legal value 

Info: "14583 ps" is a legal value 

Info: "15000 ps" is a legal value 

Info: "15417 ps" is a legal value 

Info: "15833 ps" is a legal value 

Info: "16250 ps" is a legal value 

Error (21155): Device migration enabled -- compilation may have failed due to additional constraints when migrating 

Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value of '500 ps' on node 'QSYS_46C:inst2|QSYS_46C_ddr3_control:ddr3_control|QSYS_46C_ddr3_control_pll0:pll0|pll6_phy~PLL_OUTPUT_COUNTER'. 

Info: "0 ps" is a legal value 

Info: "417 ps" is a legal value 

Info: "833 ps" is a legal value 

Info: "1250 ps" is a legal value 

Info: "1667 ps" is a legal value 

Info: "2083 ps" is a legal value 

Info: "2500 ps" is a legal value 

Info: "2917 ps" is a legal value 

Info: "3333 ps" is a legal value 

Info: "3750 ps" is a legal value 

Info: "4167 ps" is a legal value 

Info: "4583 ps" is a legal value 

Info: "5000 ps" is a legal value 

Info: "5417 ps" is a legal value 

Info: "5833 ps" is a legal value 

Info: "6250 ps" is a legal value 

Info: "6667 ps" is a legal value 

Info: "7083 ps" is a legal value 

Info: "7500 ps" is a legal value 

Info: "7917 ps" is a legal value 

Info: "8333 ps" is a legal value 

Info: "8750 ps" is a legal value 

Info: "9167 ps" is a legal value 

Info: "9583 ps" is a legal value 

Info: "10000 ps" is a legal value 

Info: "10417 ps" is a legal value 

Info: "10833 ps" is a legal value 

Info: "11250 ps" is a legal value 

Info: "11667 ps" is a legal value 

Info: "12083 ps" is a legal value 

Info: "12500 ps" is a legal value 

Info: "12917 ps" is a legal value 

Info: "13333 ps" is a legal value 

Info: "13750 ps" is a legal value 

Info: "14167 ps" is a legal value 

Info: "14583 ps" is a legal value 

Info: "15000 ps" is a legal value 

Info: "15417 ps" is a legal value 

Info: "15833 ps" is a legal value 

Info: "16250 ps" is a legal value 

Error (21155): Device migration enabled -- compilation may have failed due to additional constraints when migrating 

Error: Quartus II 64-Bit Fitter was unsuccessful. 4 errors, 1 warning 

Error: Peak virtual memory: 979 megabytes 

Error: Processing ended: Mon Jun 29 14:21:35 2015 

Error: Elapsed time: 00:00:15 

Error: Total CPU time (on all processors): 00:00:15 

 

Do you have any solution? Did I connected something wrong?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
117 Views

The phase shift of PLL is tVCO/8. 

In that case, it seems like your fVCO is 300Mhz.  

Thus each phase shift step is 417ps.  

So you wont be able to set to 500ps.
Altera_Forum
Honored Contributor I
117 Views

Which fVCO is 300MHz? 300MHz is the minimum I can set on the DDR speed... 

 

If I would like to run my Nios at 50MHz. Is it not posssible to have in this case a DDR3 RAM running with 300MHz in HardMemoryInterface? Or would it be possible with a DMA in between? 

 

What would the lowest NIOS frequency be, if I would like to habe the HardMemoryInterface?
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