Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

DDR3 validation

Honored Contributor II



I am working on DDR3 uniphy controller. I have validated the DDR3 using external memory interface tool kit. The results from external memory interface tool kit are fine.  

I am trying to do burst read and write, I am unable to see the wdata, avl_address and rdata values in signal tap ii logic analyser. Could you please provide me the solution. 

I have followed the document which is provided by the altera(emi_tut_qdr).  


Thank Regards, 

C. Ashok Reddy.
0 Kudos
0 Replies