Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12604 Discussions

DDR3 validation

Altera_Forum
Honored Contributor II
‎09-24-2015 08:59 AM
997 Views

Hi, 

 

I am working on DDR3 uniphy controller. I have validated the DDR3 using external memory interface tool kit. The results from external memory interface tool kit are fine.  

I am trying to do burst read and write, I am unable to see the wdata, avl_address and rdata values in signal tap ii logic analyser. Could you please provide me the solution. 

I have followed the document which is provided by the altera(emi_tut_qdr).  

 

Thank Regards, 

C. Ashok Reddy.
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.