I am working on DDR3 uniphy controller. I have validated the DDR3 using external memory interface tool kit. The results from external memory interface tool kit are fine. I am trying to do burst read and write, I am unable to see the wdata, avl_address and rdata values in signal tap ii logic analyser. Could you please provide me the solution. I have followed the document which is provided by the altera(emi_tut_qdr). Thank Regards, C. Ashok Reddy.