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Honored Contributor I

DDR3 without leveling clock length

Hi everyone, 


I'm developing a board with a CycloneV and a DDR3 chip drive by the HPS memory controller. CycloneV does not support write leveling. I'm currently struggling to know exactly what rules I should be following for the routing. 


On this document ( 4-9) it's stated that the clock length should be between Byte_lane_length and Byte_lane_length + 100mil. 

I saw in other documents various rules for clock routing (up to 1000mil tolerance). I don't know which one to follow in my particular case.  


Does anyone have a clear rule for clock length matching in the case of DDR3 without write leveling ? 




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Honored Contributor I

For each byte lane I routed it with DQS / DM a bit longer than DQ. 

And pretty much matched the lengths of the ck p/n to the CA lines. 

Seems to work, tests show plenty of margin. 

I have 4 16bit wide chips hooked up to the HPS DDR3, using a T topology for CA. 

The dual data are in a back to back arrangement with address mirroring. 


And 1 16bit wide DDR3 chip connected to the FPGA fabric which is point to point.