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Altera_Forum
Honored Contributor I
1,421 Views

DE0-NIOS2 clock speed limit 50MHZ

Hi, 

 

have "problem". I have DE0 dev board.  

When I load NIOS2 to fpga and use 50MHz from on board sorce. It works. 

When I try to add pll 50MHz - > works. 

But if I use more then 50MHz (pll let say 100MHz ), everything compiles but JTAG uart not giving any data back. 

 

 

I use simple Hello world program. 

 

 

Is it because I use evaluation version of Nios2 (OpenCore Plus IP is always on).
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7 Replies
Altera_Forum
Honored Contributor I
52 Views

You should check if the Timing analysis pass to look what is the maximum frequency allowed.

Altera_Forum
Honored Contributor I
52 Views

Hi, 

 

Thanks for fast reply. 

 

Yes, fmax limit to 60mhz. But I use f type core, 4 level pipeline. 

Could different type of pll resolve the problem???? 

 

Report gives me note : limi due to high minimum pulse width violation (tcl)
Altera_Forum
Honored Contributor I
52 Views

Hi, 

it doesn't only depend of the NIOS2 core but of all what's driven by this clock. 

Did you use the pll compensation for that clock ? 

on the pll megawizard : "1 Paramter settings - General/Modes - which output clock will be compensated for ?" 

Then, if you have a big archietcture, you can split it on different clock domains depending on your critical path, so that the cpu clock can be raised higher.
Altera_Forum
Honored Contributor I
52 Views

In Timequest, have a look at the top failing paths. It will give you an indication on what parts to optimize to increase the fmax. In some SOPC systems you need to add some pipeline bridges on the critical paths. 

Using the timing advisor (Tools menu) will also give you indications on what parameters you can change to increase the fmax.
Altera_Forum
Honored Contributor I
52 Views

Hi, 

 

I have used all pll types - it does not increase speed. Just give variation fort 10 ish mhz.  

I have looked at recommendations, same result. What else could increase speed.  

I use default constrains ( if the is any :) ). Should I apply custom constrains? 

Sorry I am very new in FPGA design.  

In reports I see that all slack's are positive, with back up.
Altera_Forum
Honored Contributor I
52 Views

Hi, 

how did you apply the recommendations? Maybe we can have a look at your SOPC or Qsys design ? 

What is the component concerned with the top failing path when you increase frequency so that the constraints are no more satisfied ? 

You can try a minimal design where only Nios2 is present with JTAG SysID and external or even internal RAM, that will allow you to know what Fmax your Nios2 can reach on DE0.
Altera_Forum
Honored Contributor I
52 Views

Hi, 

 

I think I have solved the problem. I used in sdc file "derive_pll_clocks -create_base_clocks" instead off manual pll creation and it works. 275 fmax (in qsys I have left cpu +pll +sysid + clock_in. 

 

Thank you for replay's guys.
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