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Altera_Forum
Honored Contributor I
1,012 Views

DE0-Nano EPCS Nios II problem

Hi all, 

 

I know this question has been asked many times, but I did a lot of searching and followed few tutorials and still couldn't make it to work on DE0-Nano. 

 

I want to save both hardware and Nios II software in EPCS so that the system will run after power up. I know my project works, because it runs without problem if I load the hardware through USB blaster and run the Nios II software from on-chip memory. I understand in order to run Nios II SW from EPCS I first need to include an epcs_flash_controller in the Qsys project and change the CPU reset vector memory to EPCS. 

 

I've tried the following two methods to download HW/SW to EPCS, but only the HW part works, SW doesn't. 

 

Method 1: using Nios II command shell 

I ran the following commands in the command shell 

 

sof2flash --epcs --input=nios2_quartus2_project.sof --output=hw.flash --verbose 

elf2flash --input=count.elf --output=sw.flash --epcs --after=hw.flash --verbose 

nios2-elf-objcopy -I srec -O ihex hw.flash hw.hex 

nios2-elf-objcopy -I srec -O ihex sw.flash sw.hex 

 

Then I used the Quartus II Convert Programming File tool to create a JIC file with the hex files created above. And used the Quartus II programmer to program this JIC file to DE0-Nano. After power reset, the HW works but SW doesn't. 

 

Method 2: Nios II Flash Programmer 

In Nios II Flash Programmer I simply added SOF and ELF files to the program and press the start button. The result is the same. HW works, but SW doesn't. 

 

Can anyone tell me what I did wrong? 

 

And here is another question. From both of the methods above, the programmer first writes the HW to EPCS at address 0x00, then immediately followed by SW hex. Although the CPU's reset vector memory is set to EPCS, but how does it know where the software instructions start at? It is not at 0x00. 

 

Thank you!
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7 Replies
Altera_Forum
Honored Contributor I
90 Views

Hi, 

 

I think you have not set the Nios II reset vector to an address where the software instruction starts. You will need to set the reset vector offset to where your software starts.
Altera_Forum
Honored Contributor I
90 Views

 

--- Quote Start ---  

Hi, 

 

I think you have not set the Nios II reset vector to an address where the software instruction starts. You will need to set the reset vector offset to where your software starts. 

--- Quote End ---  

 

 

The tutorials that I looked at didn't talk about setting the reset vector offset. I only know the SW instruction data starts right after the HW configuration data. But how do I find out exactly where it is at?
Altera_Forum
Honored Contributor I
90 Views

Hi, 

 

Please refer to AN736 page 3 for flash layout and page 6 for setting reset vector. 

You can determine the minimum reset vector offset by using the following equation: 

minimum reset vector offset = (.sof image start address + .sof image size) in HEX
Altera_Forum
Honored Contributor I
90 Views

AN736 talks about EPCQ, not EPCS. 

Couple days ago, I found UG-20001 Generic Nios II Booting Methods User Guide. And on page 11 it has a section about "Nios II Processor Application Copied from EPCS Flash to RAM Using Boot Copier". 

 

"The EPCS address space is not mapped into the Altera Avalon EPCS Flash Controller’s Avalon MM slave interface. Instead, read or write accesses are done through CSRs. Upon system reset, the EPCS device 

needs to be initialized before usage. For these reasons, the EPCS controller-based boot copier is required for initializing the EPCS device and copying the Nios II application to RAM for execution. The EPCS controller instantiates a block of boot ROM internally at its base address (offset 0x0, just before EPCS controller’s CSRs) for storing the boot copier. Nios II reset vector offset must set to EPCS controller base address, such that upon system reset the boot copier is executed first to initialize the EPCS controller and device." 

 

So the reset vector memory should set to EPCS controller and the reset vector offset should set to 0x00. I still don't know what I have done wrong.
Altera_Forum
Honored Contributor I
90 Views

The EPCQ flow is same as EPCS. I would suggest you follow the instructions in AN736 and replace the Legacy EPCS Controller with Altera Serial Flash Controller. 

Setting reset vector offset to 0x0 is definitely not right for your case as the SOF file has been stored at location 0x0. 

These documentations will be updated/integrated eventually :)
Altera_Forum
Honored Contributor I
90 Views

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Altera_Forum
Honored Contributor I
90 Views

 

--- Quote Start ---  

AN736 talks about EPCQ, not EPCS. 

Couple days ago, I found UG-20001 Generic Nios II Booting Methods User Guide. And on page 11 it has a section about "Nios II Processor Application Copied from EPCS Flash to RAM Using Boot Copier". 

 

"The EPCS address space is not mapped into the Altera Avalon EPCS Flash Controller’s Avalon MM slave interface. Instead, read or write accesses are done through CSRs. Upon system reset, the EPCS device 

needs to be initialized before usage. For these reasons, the EPCS controller-based boot copier is required for initializing the EPCS device and copying the Nios II application to RAM for execution. The EPCS controller instantiates a block of boot ROM internally at its base address (offset 0x0, just before EPCS controller’s CSRs) for storing the boot copier. Nios II reset vector offset must set to EPCS controller base address, such that upon system reset the boot copier is executed first to initialize the EPCS controller and device." 

 

So the reset vector memory should set to EPCS controller and the reset vector offset should set to 0x00. I still don't know what I have done wrong. 

--- Quote End ---  

 

 

Hey nice2meet_you , I m having the same problem , so have u solved it yet ?
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