Honored Contributor II
09-27-2013 11:15 PM
Hey all,Obviously this is my first post, I've been working on a DE0-Nano LCD controller to drive an antiquated parallel interface display that I robbed from a TI TravelMate 4000 laptop (made many eons ago!). I understand the timing sequences well, and (conceptually) understand how they could be implemented, but as this is one of my first FPGA projects, I'm lacking on the Verilog/HDL experience to know how to implement it correctly - as well as other issues surround the Nios II processor. For the "floorplan" of the controller I was going to have a Nios II processor integrated that takes data off USB serial and puts it to RAM - specifically, three serial bytes per pixel, of which in those bytes only the 3 least-significant bytes are important. The RAM will act as a buffer to hold all the data, or at least that's what my mind thinks its purpose is! After all image data has been transferred, the processor will assert a line, suppose it's called START#, to the logic interface to tell it to pull the data off RAM and do the signal synchronization to output. Does that jive with generally how you guys would go about something of this sort? Being natively an iOS and Windows (software) programmer the idea of coding hardware is putting my logic on its head. There are a few things I had questions about, mainly due to my completely fish-outta-water status in hardware coding:
- Obviously, delays such as# whatever aren't synthesizeable. I was originally thinking of implementing this as a counting register, and incrementing it by one on posedge clocks, of course using non-blocking equalities to ensure that the code times properly. Is that the appropriate way to go about this?
- When I go about writing the C/C++ behavior file for the Nios II (not sure what it's called specifically, have to go back and look in the Qsys docs) how do I access RAM/write to it?