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Altera_Forum
Honored Contributor I
1,284 Views

DE0-Nano-SoC DDR3 Access using Nios-2

My intention is to put a simple assembly code into the DDR3 on the DE0-Nano-SoC board and use the Nios II to access that code and run it using the altera monitor program. 

 

I want to access the DDR3 using the Nios II on the DE0-Nano-SoC board. The tutorial on the altera website is for DE0-Nano board and is not working. When I select the SDRAM clock in Qsys, there are only 4 pins (clock source, reset source, system clock and reset). The sdram_clk signal is missing. How do I resolve this problem? 

 

Is it necessary to make use of the FPGA-Bridge and only then access the the DDR3? I have followed a tutorial on altera tutorials which teaches how to use the SDRAM. I followed it exactly but I am unable to get the result. It gives me an error in altera monitor program saying: 

 

Using cable "USB-BlasterII [1-1.1]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused
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Altera_Forum
Honored Contributor I
41 Views

I hope you're not confusing 'Nios' with the Hard Processor System (HPS) in the FPGA on the DE0-Nano-SoC board... 

 

The DDR3 on the DE0-Nano-SoC board is connected to the HPS, not the FPGA fabric where a Nios might be. Whilst some HPS peripheral can be mapped to the FPGA fabric, the DDR3 interface can't. So, you can't 'use the nios ii to access that code' if it's in DDR3, not without having software running in the HPS which then presents the DDR3 data to the fabric via an AXI interface. 

 

I'm afraid it's not suprosing the tutorial for the DE0-Nano board isn't working on the DE0-Nano-SoC board. They're quite different beasts. 

 

Cheers, 

Alex