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Altera_Forum
Honored Contributor I
901 Views

DE0-Nano and I2C Opencores Issues

Finally had a chance sit down and play around with DE0-Nano. I am using Quartus/Qsys 11.1 and Nios II 11.1 Software build tools. 

 

I thought as a relatively quick project I would experiment using the opencores I2C master downloaded from alterawiki.com/wiki/I2C_(OpenCores) to interface with the ADXL345 accelerometer and 24LC02B eeprom ICs on the DE0-Nano board. 

 

The first problem I hit was with the version of Qsys required by the I2C master (12.0 vs 11.1). I simply used the 'New component' wizard in Qsys to generate the new _hw.tcl file with the following wishbone to avalon bus signal assignments: 

 

 

wb_clk_i --- clk 

wb_rst_i --- reset 

wb_adr_i --- address 

wb_we_i --- write 

wb_ack_o --- waitrequrest_n 

wb_dat_i --- writedata 

wb_dat_o --- readdata 

wb_stb_i --- chipselect 

wb_inta_o --- irq 

scl_pad_io --- export 

sda_pad_io --- export 

 

I then made the following pin assignments 

 

scl_pad_io == PIN F2 (output) 

sda_pad_io == PIN F1 (bi-dir) 

 

PIN G5 (G_SENSOR_CS_N) I tied to VCC to ensure the accelerometer is in I2C mode rather than SPI mode. 

 

I had a few more niggles after this, specifically getting the driver to be recognised by Nios II IDE. Turns out I had to rename all instances of opencores_I2C to I2C_opencores in the _sw.tcl file. 

 

Now I have the following code which is running on the DE0-Nano, which should write 0x55 to the first byte of the eeprom and read back the same byte as a second I2C transaction. The eeprom 7-bit address should be 0x50 (assuming I have found the correct datasheet). The software functions are defined with I2C_opencores available from the link above. 

 

//Intialise I2C master controller at 100kHz, 50MHz Cpu clock. 

I2C_init(I2C0_BASE,ALT_CPU_CPU_FREQ,100000); 

 

// Write 0x55 to location 0x0 for I2C device at 0x50 (22LC02B) 

I2C_start(I2C0_BASE,0x50,0); 

I2C_write(I2C0_BASE,0x0,0); 

I2C_write(I2C0_BASE,0x55,1); 

 

// Write address that is to be read from 

I2C_start(I2C0_BASE,0x50,0); 

I2C_write(I2C0_BASE,0x0,0); 

 

 

// Read from the device 

I2C_start(I2C0_BASE,0x50,1); 

data = I2C_read(I2C0_BASE,1); 

printf("Data: 0x%x \n",data); 

 

 

However I get the following console output if I defined I2C_DEBUG... 

 

Initializing I2C at 0x40040b0,  

with clock speed 0x2faf080  

and SCL speed 0xc350  

and prescale 0xc7 

 

 

Start I2C at 0x40040b0,  

with address 0x50  

and r/w 0x0  

NOACK 

 

 

Write I2C at 0x40040b0,  

with data 0x0, 

with last 0x0 

ACK 

 

 

Write I2C at 0x40040b0,  

with data 0x55, 

with last 0x1 

ACK 

 

 

Start I2C at 0x40040b0,  

with address 0x50  

and r/w 0x0  

NOACK 

 

 

Write I2C at 0x40040b0,  

with data 0x0, 

with last 0x0 

ACK 

 

 

Start I2C at 0x40040b0,  

with address 0x50  

and r/w 0x1  

NOACK 

 

 

Read I2C at 0x40040b0,  

with last 0x1 

 

 

Data: 0x50dc5a0f 

 

 

What I don't understand is why I am getting an NOACK response from the start transaction, but do get an ACK response from the following write transaction. Without a scope/logic analyser I am a bit stuck as to what could be going wrong. 

 

Hope there is someone out there who has had a similar experience to me and will be able to help me out. 

 

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3 Replies
Altera_Forum
Honored Contributor I
77 Views

Hi there, 

 

I'm working on the adxl345 on DE0-nano board for my university project, 

and I have the same problems with My nios program in eclipse IDE . 

I'm using Quartus 11.1 and I will appreciating if you send me the programs. 

when I run the program It does not even start the transmitting and I suspect my sw.tcl or one other file is corrupted by the changes that I did to those files, 

Anybody knows how can I run this core into my design?? 

I'd appreciating if somebody help me. 

 

farshid_mfc[at]yahoo.com
Altera_Forum
Honored Contributor I
77 Views

H there, 

 

I have taken a module from http://www.eewiki.net/display/logic/i2c+master+%28vhdl%29 when integrating to the Avalon bus i have had some issues. This is not wishbone compliant and my plan was to write my own wrapper but with time running out i was an unit testing needed i was wondering if; 

 

Altera supply a bus similar to that of the clock crossing bridge?  

 

Thanks
Altera_Forum
Honored Contributor I
77 Views

Hi there, 

 

I have a DE0 Nano as well, and I am using the same versions of Quartus/Qsys and Nios II, but for some reason I dont have any signal at the scl_pad_io or sda_pad_io pins (they are asssigned to pins on the GPIO header). I know it's been a long while since this thread was last active, but if you could help me I would appreciate it a lot :) 

 

Cheers, 

Salman
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