DE2-115 Ethernet not working

[Altera_Forum]

Hi , 

 I was trying to run DE2-115 example of loop back test using Ethernet from this document " Using Triple-Speed Ethernet on DE2-115 Boards".   I got it to work , but i dont get any messages received, although i used both cross-over cable and normal Ethernet cable .  I created its software by starting a new hello world project and copied the tse_tutorial code into main , it compiled without errors .   See screen shot attached .  Regards ,  code :  # include <altera_avalon_sgdma.h># include <altera_avalon_sgdma_descriptor.h># include <altera_avalon_sgdma_regs.h> # include "sys/alt_stdio.h"# include "sys/alt_irq.h"# include <unistd.h> // Function Prototypes void rx_ethernet_isr (void *context); // Global Variables unsigned int text_length; // Create a transmit frame unsigned char tx_frame = { 0x00,0x00, // for 32-bit alignment 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // destination address (broadcast) 0x01,0x60,0x6E,0x11,0x02,0x0F, // source address 0x00,0x2E, // length or type of the payload data '\0' // payload data (ended with termination character) }; // Create a receive frame unsigned char rx_frame = { 0 }; // Create sgdma transmit and receive devices alt_sgdma_dev * sgdma_tx_dev; alt_sgdma_dev * sgdma_rx_dev; // Allocate descriptors in the descriptor_memory (onchip memory) alt_sgdma_descriptor tx_descriptor __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor tx_descriptor_end __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor rx_descriptor __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor rx_descriptor_end __attribute__ (( section ( ".descriptor_memory" ))); /******************************************************************************** * This program demonstrates use of the Ethernet in the DE2-115 board. * * It performs the following: * 1. Records input text and transmits the text via Ethernet after Enter is * pressed * 2. Displays text received via Ethernet frame on the JTAG UART ********************************************************************************/ int main(void) { // Open the sgdma transmit device sgdma_tx_dev = alt_avalon_sgdma_open ("/dev/sgdma_tx"); if (sgdma_tx_dev == NULL) { alt_printf ("Error: could not open scatter-gather dma transmit device\n"); return -1; } else alt_printf ("Opened scatter-gather dma transmit device\n"); // Open the sgdma receive device sgdma_rx_dev = alt_avalon_sgdma_open ("/dev/sgdma_rx"); if (sgdma_rx_dev == NULL) { alt_printf ("Error: could not open scatter-gather dma receive device\n"); return -1; } else alt_printf ("Opened scatter-gather dma receive device\n"); // Set interrupts for the sgdma receive device alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) rx_ethernet_isr, 0x00000014, NULL ); // Create sgdma receive descriptor alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, rx_frame, 0, 0 ); // Set up non-blocking transfer of sgdma receive descriptor alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor ); // Triple-speed Ethernet MegaCore base address volatile int * tse = (int *) 0x00102000; // Initialize the MAC address *(tse + 3) = 0x116E6001; *(tse + 4) = 0x00000F02; // Specify the addresses of the PHY devices to be accessed through MDIO interface *(tse + 0x0F) = 0x10; *(tse + 0x10) = 0x11; // Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback *(tse + 0x94) = 0x4000; // Write to register 16 of the PHY chip for Ethernet port 1 to enable automatic crossover for all modes *(tse + 0xB0) = *(tse + 0xB0) | 0x0060; // Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk *(tse + 0xB4) = *(tse + 0xB4) | 0x0082; // Software reset the second PHY chip and wait *(tse + 0xA0) = *(tse + 0xA0) | 0x8000; while ( *(tse + 0xA0) & 0x8000 ) ; // Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding *(tse + 2) = *(tse + 2) | 0x0000004B; alt_printf( "send> " ); text_length = 0; while (1) { char new_char; tx_frame = '\0'; // Add new typed characters to the transmit frame until the user types the return character while ( (new_char = alt_getchar()) != '\n' ) { if (new_char == 0x08 && text_length > 0) { // Check if character is a backspace and if there is anything to delete alt_printf( "%c", new_char ); text_length--; // Maintain the terminal character after the text tx_frame = '\0'; } else if (text_length < 45) { // Check if there is still room in the frame for another character alt_printf( "%c", new_char ); // Add the new character to the output text tx_frame = new_char; text_length++; // Maintain the terminal character after the text tx_frame = '\0'; } } alt_printf( "\nsend> " ); text_length = 0; // Create transmit sgdma descriptor alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, tx_frame, 62, 0, 1, 1, 0 ); // Set up non-blocking transfer of sgdma transmit descriptor alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor ); // Wait until transmit descriptor transfer is complete while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0) ; } return 0; } /**************************************************************************************** * Subroutine to read incoming Ethernet frames ****************************************************************************************/ void rx_ethernet_isr (void *context) { int i; // Wait until receive descriptor transfer is complete while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0) ; // Clear input line before writing for (i = 0; i < (6 + text_length); i++) { alt_printf( "%c", 0x08 ); // 0x08 --> backspace } // Output received text alt_printf( "receive> %s\n", rx_frame + 16 ); // Reprint current input line after the output alt_printf( "send> %s", tx_frame + 16 ); // Create new receive sgdma descriptor alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, rx_frame, 0, 0 ); // Set up non-blocking transfer of sgdma receive descriptor alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor ); }

[Altera_Forum]

I didn't look at the code in detail, but it doesn't look like a complete TCP/IP stack. That demo just shows basic passing of data from one Ethernet port to the other. The initializing code is for loop back, not passing packets through. Look at driver code for other boards that use this phy chip as an example of how to set it up. Note that different phy chips were used on the DE series boards, depending on how old they are. Make sure the code you are using matches the phy chip, and that it is for communication not just loop back testing.

[Altera_Forum]

Thats another major issue i have been sending emails to the distributors and manufacturer (i.e Marvell Semiconductor) of the PHY Chip : 88E1111 which is on DE2-115 board for about two weeks to send me interface information about this chip , but none of them reply back . I can write up my own VHDL code for the interface but i need setup and hold times info . Even Terasic did helped me .

[Altera_Forum]

Neither Mervell nor Terasic are likely to answer to your direct emails, since all the interface information you need can be easily found and downloaded from their websites. 

I also believe your DE2-115 has been delivered with a few reference designs and sample code for Ethernet communication.

[Altera_Forum]

There is no interface information on either's website its just a "Product Brief " , yes there are examples designs in the DE2-115 CD , but i need a simple design and the one i mentioned above is the simplest i.e " Using Triple-Speed Ethernet on DE2-115 Boards". , which is not working at least on my computer . And my main goal is to write my own VHDL to interface with 88E1111 .

[Altera_Forum]

The 88E1111 is proprietary to Marvell. If you work for a company that is developing a product that uses it, you can contact your distributor to set up a NDA. This isn't available to individuals or universities as far as I know.  

 Terasic isn't allowed to give that information out because of their NDA. Check to see if there are any timing constraints with the Ethernet examples. They should be reusable. You might also look at Linux kernel sources to see if you can get an initialization sequence for the PHY. I've worked with that chip and its versatile, but complex. I wouldn't want to try to get it going without the documentation.

[Altera_Forum]

During debugging i.e single stepping, i have noticed that Nios IDE hangs at this line in the above code : // Create sgdma receive descriptor alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, rx_frame, 0, 0 );  

 And underneath it says that : warning incompatible pointer types ????  Where as these pointers are defined over here :   // Allocate descriptors in the descriptor_memory (onchip memory) alt_sgdma_descriptor tx_descriptor __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor tx_descriptor_end __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor rx_descriptor __attribute__ (( section ( ".descriptor_memory" ))); alt_sgdma_descriptor rx_descriptor_end __attribute__ (( section ( ".descriptor_memory" )));    I cantt seem to find out where and in which file these are defined ????  i have looked into system.h file and found this :   /* * descriptor_memory configuration * */ # define ALT_MODULE_CLASS_descriptor_memory altera_avalon_onchip_memory2 # define DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 # define DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 # define DESCRIPTOR_MEMORY_BASE 0x100000 # define DESCRIPTOR_MEMORY_CONTENTS_INFO "" # define DESCRIPTOR_MEMORY_DUAL_PORT 0 # define DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO" # define DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "DE2115_Ethernet_descriptor_memory" # define DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 1 # define DESCRIPTOR_MEMORY_INSTANCE_ID "NONE" # define DESCRIPTOR_MEMORY_IRQ -1 # define DESCRIPTOR_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1 # define DESCRIPTOR_MEMORY_NAME "/dev/descriptor_memory" # define DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 # define DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "AUTO" # define DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" # define DESCRIPTOR_MEMORY_SINGLE_CLOCK_OP 0 # define DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1 # define DESCRIPTOR_MEMORY_SIZE_VALUE 4096 # define DESCRIPTOR_MEMORY_SPAN 4096 # define DESCRIPTOR_MEMORY_TYPE "altera_avalon_onchip_memory2" # define DESCRIPTOR_MEMORY_WRITABLE 1    I dont see any dev directory or file with name : DE2115_Ethernet_descriptor_memory , can any one guide me how to remove this warning ????

[Altera_Forum]

The incompatible pointer warning is probably due to the fact rx_frame is unsigned char pointer, while the api function requires alt_u32*. 

Anyway this is not likely to cause the processor to hang. I think you'd rather have a major problem in your bus system.  My guesses are: - timing failing for some paths related to dma - missing bus connections; i.e. descriptor memory must be connected both to nios data port and to sdgma master port.

[Altera_Forum]

During Qsys project generation , i see some warnings , see screen shots attached .  

 It says sgdma_rx.descriptor_read must be connected to an Avalon-MM slave .  But i followed the reference doc .

[Altera_Forum]

You are definitely missing the required connections. 

Descriptor read and write master ports must be both connected to descriptor memory slave port. sgdma streaming in/out ports must be connected to rx/tx ports of tse mac component.