Re: DE2-115: Problem - ISP1362 Does Not Work

Altera_Forum · ‎05-18-2012

Hi guys,

I am using DE2-115 board configured with SOPC file from included DE2-115 CD (DE2_115_NIOS_DEVICE_LED).

I removed all components except the following:

- pll

- jtag_uart

- cpu

- onchip_memory

- sdram

- clock_crossing_io

- timer

- sysid

- usb

I made some changes on the remaining components as below (SOPC screenshot attached):

1. cpu

- enable hardware divide

- reset & exception vector: memory: sdram

- include mmu

- fast TLB miss exception vector: memory: onchip_memory

- include tightly coupled instruction & data master ports

2. onchip_memory

- enable dual port access

- total memory size: 1024 bytes

3. usb

- changed name to ISP1362

This is the content of DTS file generated:

/*
 * This devicetree is generated by sopc2dts
 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
 * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
 */
/dts-v1/;
/ {
	model = "ALTR,DE2_115_SOPC";
	compatible = "ALTR,DE2_115_SOPC";
# address-cells = < 1 >;
# size-cells = < 1 >;
	cpus {
	# address-cells = < 1 >;
	# size-cells = < 0 >;
		cpu: cpu@0x0 {
			device_type = "cpu";
			compatible = "ALTR,nios2-11.1";
			reg = < 0x00000000 >;
			interrupt-controller;
		# interrupt-cells = < 1 >;
			clock-frequency = < 100000000 >;	/* embeddedsw.CMacro.CPU_FREQ type NUMBER */
			dcache-line-size = < 32 >;	/* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */
			icache-line-size = < 32 >;	/* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */
			dcache-size = < 2048 >;	/* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */
			icache-size = < 4096 >;	/* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */
			ALTR,implementation = "fast";	/* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/
			ALTR,pid-num-bits = < 8 >;	/* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */
			ALTR,tlb-num-ways = < 16 >;	/* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */
			ALTR,tlb-num-entries = < 256 >;	/* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */
			ALTR,tlb-ptr-sz = < 8 >;	/* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */
			ALTR,has-div;	/* embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT type NUMBER*/
			ALTR,has-mul;	/* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/
			ALTR,reset-addr = < 0xc0000000 >;	/* embeddedsw.CMacro.RESET_ADDR type NUMBER */
			ALTR,fast-tlb-miss-addr = < 0xc9001000 >;	/* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */
			ALTR,exception-addr = < 0xc0000020 >;	/* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */
		}; //end cpu@0x0 (cpu)
	}; //end cpus
	memory@0 {
		device_type = "memory";
		reg = < 0x00000000 0x08000000
			0x09001000 0x00000400 >;
	}; //end memory@0
	sopc@0 {
		ranges;
	# address-cells = < 1 >;
	# size-cells = < 1 >;
		device_type = "soc";
		compatible = "ALTR,avalon", "simple-bus";
		bus-frequency = < 100000000 >;
		clock_crossing_io: bridge@0x8000000 {
			compatible = "ALTR,avalon-11.1", "simple-bus";
			reg = < 0x08000000 0x00000040 >;
		# address-cells = < 1 >;
		# size-cells = < 1 >;
			ranges = < 0x00000000 0x08000000 0x00000020
				0x00000020 0x08000020 0x00000008 >;
			timer: timer@0x0 {
				compatible = "ALTR,timer-11.1", "ALTR,timer-1.0";
				reg = < 0x00000000 0x00000020 >;
				interrupt-parent = < &cpu >;
				interrupts = < 0 >;
				clock-frequency = < 10000000 >;
			}; //end timer@0x0 (timer)
			sysid: sysid@0x20 {
				compatible = "ALTR,sysid-11.1", "ALTR,sysid-1.0";
				reg = < 0x00000020 0x00000008 >;
			}; //end sysid@0x20 (sysid)
		}; //end bridge@0x8000000 (clock_crossing_io)
		jtag_uart: serial@0x9001410 {
			compatible = "ALTR,juart-11.1", "ALTR,juart-1.0";
			reg = < 0x09001410 0x00000008 >;
			interrupt-parent = < &cpu >;
			interrupts = < 1 >;
		}; //end serial@0x9001410 (jtag_uart)
		pll: clock@0x9001400 {
			compatible = "ALTR,pll-11.1", "ALTR,pll-1.0";
			reg = < 0x09001400 0x00000010 >;
		}; //end clock@0x9001400 (pll)
		ISP1362: isp1362@0x9001418 {
			compatible = "nxp,isp1362-1.0", "nxp,usb-isp1362";
			reg = < 0x09001418 0x00000004
				0x0900141C 0x00000004
				0x09001420 0x00000004
				0x09001424 0x00000004 >;
			interrupt-parent = < &cpu >;
			interrupts = < 2 3 >;
		}; //end isp1362@0x9001418 (ISP1362)
	}; //end sopc@0
	chosen {
		bootargs = "debug console=ttyAL0,115200";
	}; //end chosen
};

I made kernel configuration as below:

- platform options

=> enable MULX instruction

=> enable DIV instruction

- device driver

=> SCSI device support

=> SCSI disk support

=> USB support

=> Support for host-side USB

=> USB device filesystem

=> ISP1362 HCD support

=> USB mass storage support

- File Systems

=> Ext3 journalling file system support

=> DOS/FAT/NT Filesystems

=> MSDOS fs support

=> VFAT (Windows-95) fs support

=> Native language support

=> codepage 437

=> NLS ISO 8859-1

I successfully made the image and load into DE2-115 board, but there is where problem occurs:

Condition# 1.

If I exclude isp1362 in both sopc & kernel configuration, nios2-linux starts up normally, but with garbage characters occasionally displayed when starting up nios2-linux.

Condition# 2.

If I include isp1362 in both sopc & kernel configuration, it is downloaded to the board and verified successfully, but then just hang at there, nothing more comes out in nios2-terminal, nios2-linux fails to start up.

Any advice regarding this matter? Thanks!

Regards,

Gladion

Altera_Forum · ‎05-22-2012

Hi,

Your hardware meets the timing ? How about the clock phase shift for sdrams ?

Kazu

Altera_Forum · ‎05-23-2012

Hi,

Thanks for your reply. I use the default hardware timing configured in the reference design.

For ISP 1362:

hc (connected to data master)

Setup: 140ns

Read wait: 50ns

Write wait: 50ns

Hold: 140ns

dc (connected to data master)

Setup: 150ns

Read wait: 150ns

Write wait: 150ns

Hold: 150ns

I did try to change all parameter values to 100ns as described in altera wiki, but still failed.

For sdram:

Clock frequency: 100MHz

Clock phase shift: -65 deg

Oh yes, there is 1 more thing. If I only use Nios II without MMU, and compiled using older version of Nios II Linux, the USB works properly.

Any idea regarding this situation? Thanks! ^^

Regards,

Gladion

Altera_Forum · ‎05-23-2012

Hi,

--- Quote Start ---

For sdram:

Clock frequency: 100MHz

Clock phase shift: -65 deg

--- Quote End ---

Maybe the timing for sdrams is OK, and the timing for ISP 1362 will not affect the booting. But did you set the processor starting address at 0xc100000?


Downloaded 4199KB in 90.1s (46.6KB/s)
Verified OK
Starting processor at address 0xC1000000
nios2-terminal ......

Anyway I'm making a "Try Out Example" for Terasic's tPad, and going to upload those to Altera Wiki. In those, ISP 1329 Host is working well and I can plug keyboards, mouse, USB memory and etc. successfully. Would you please wait a moment ?

Kazu

Altera_Forum · ‎05-23-2012

--- Quote Start ---

I made kernel configuration as below:

- platform options

=> enable MULX instruction

--- Quote End ---

MULX? did you enable this in your processor?

Altera_Forum · ‎05-24-2012

Hi,

Kazuyasu:

Well, I leave it to that one to default setting, since it usually works in this way.

Hmm, will try on this and tell you guys about the results. ^^

ykozlov:

Yup, I did. Isn't it has to be enabled if hardware divide option is enabled in Nios II processor?

Thanks and regards,

Gladion

Altera_Forum · ‎05-24-2012

Hi,

--- Quote Start ---

Well, I leave it to that one to default setting, since it usually works in this way.

Hmm, will try on this and tell you guys about the results. ^^

--- Quote End ---

I'm using the old '20080619' version sources which Wind River guys threw to Nios Wiki community.This version has many problems around mmu's macros and we can't select the main memory base address freely except 0xc0000000. Of cource, I don't know that the latest version improves these or not, but I recommend you to delete the residual offset.

Kazu

Altera_Forum · ‎05-24-2012

--- Quote Start ---

ykozlov:

Yup, I did. Isn't it has to be enabled if hardware divide option is enabled in Nios II processor?

Thanks and regards,

Gladion

--- Quote End ---

MULX is 64-bit Multiply and is different from MUL. I don't think it's related to DIV.

If you have an instruction enabled in your build that the processor doesn't have, you're going to run into problems.

Altera_Forum · ‎05-25-2012

Hi guys,

Kazuyasu:

I tried changing the processor starting address to 0xC1000000, but still results in the same, even sometimes it refused to load image. There are times when same configurations but just recompilation even cause kernel panic.

Would you send me any SOPC design of yours on DE2-115 as reference for me? Because I did follow the same steps described in Altera Wiki but still failed~ ><

ykozlov:

Hmm, I disabled the hardware divide option and uncheck MULX instruction in kernel configuration menu, yet the usb still not functioning. I think this is not the one which affects the functionality of isp1362.

Thanks and regards,

Gladion

Altera_Forum · ‎05-25-2012

Hi Kazuyasu,

I tried to load with your image, and seems that there's no problem with the hardware.

Thanks for the attachment. ^^

Anyway, will refer to your configuration and compare to see where I went wrong, since you are using Quartus 9.1, and I am using version 11.0.

Thanks and regards,

Gladion

Altera_Forum · ‎05-30-2012

Hi guys,

Thanks a lot for the attachment, seems working on my board, means it's no problem with the hardware.

Regards,

Gladion