I'm trying to get my hardware/software nios project into the EPCS64 device on the DE2-115 board. It sounds like I need a EPCS controller in my nios project, but when it exports the signals for the controller I can't find the pins in the schematics I'm supposed to connect them to. Where do you find the pins for the EPCS device on this board?I'm following this tutorial: http://www.altera.com/support/kdb/downloads/rd11122013_865/nios%20ii%20boot%20from%20epcq%20and%20ep... It seems like the hardware design is getting in there, but not the software and I think it's because I am unable to assign my reset vector to the EPCS controller without knowing what pins on the FPGA to use.
The EPCS device pins are fixed, i.e., you have no choice as to their pin assignments. The EPCS device is used for Active Serial (AS) configuration, and then once the FPGA enters user-mode, you can access the EPCS device as user SPI flash. If you add the Altera EPCS flash IP core into your design, eg., Qsys, I don't think you need to make any pin assignments, otherwise you can just look at the pin planner view and note which pins correspond to the AS pins and use those in your assignments. Sometimes the Terasic schematics do not show the configuration device page (since it also includes the USB-Blaster circuit).Cheers, Dave
ohhhhh...ok. I exported the pins not even thinking about that. Got ya. So should I just not export the "external signals"? Pic of the epcs module in Qsys is attached to show what I"m talking about. If I do export those I'll have to do what you said and find the pins.https://www.alteraforum.com/forum/attachment.php?attachmentid=9469
--- Quote Start --- So should I just not export the "external signals"? Pic of the epcs module in Qsys is attached to show what I"m talking about. If I do export those I'll have to do what you said and find the pins. --- Quote End --- I don't use the Altera IP, so normally I assign the pins explicitly. Go ahead and try not exporting the pins and see if the tool assigns the pins directly. You can have a look at the .pin file or Pin Planner after place-and-route, or look at the RTL Netlist viewer, and you'll be able to tell if your EPCS controller connects to the pins correctly. Cheers, Dave
So far I've found 3/4 pins. The SCE pin is giving me some problems. Do you know where to find it? I have the pin out and Pin information sheets where I found data0, dclk and sdo, but no SCE pin.
--- Quote Start --- So far I've found 3/4 pins. The SCE pin is giving me some problems. Do you know where to find it? I have the pin out and Pin information sheets where I found data0, dclk and sdo, but no SCE pin. --- Quote End --- I just looked at the Pin Planner for a DE0-nano design, and here are the names you are looking for ... epcs_csN = nCSO epcs_sck = DCLK epcs_mosi = ASDO/DATA1 epcs_miso = DATA0 Cheers, Dave
Hey Dave,Thanks for the info. I finally found them. When I added the EPCS controller to my Qsys project and synthesized it the EPCS controller generated 4 external signals. They are called data0, dclk, sce and sdo. I found all of the pins in the Pin information pdf and Cyclone IV pinout pdf with the exception of sce. I think that is the nCSO though which I also found in there as CSO. So I've gotten all of those connected up now and I've still got a problem. Maybe I can post up my process and you can let me know if you see anything I'm missing because for some reason I can't bootload the nios code. This first way (JIC File) - from the attached NiosII Boot from EPCQ and EPCS in QuartusII 13.0: First I run sof2flash() sof2flash --input="D:/projects/xyz/DE2-115/Onboard_UART_Test/output_files/OnBoardUartTest.sof" --output="D:/projects/xyz/DE2-115/Onboard_UART_Test/flash/hw.flash" --epcs --verbose next i run elf2flash: elf2flash --input="D:\projects\xyz\DE2-115\Onboard_UART_Test\software\DE115_OnBoard_UART\DE115_OnBoard_UART.elf" --output="D:\projects\xyz\DE2-115\Onboard_UART_Test\flash\sw.flash" --epcs --after="D:\projects\MMT\DE2-115\Onboard_UART_Test\flash\hw.flash" --verbose next I run nios2-elf-objcopy: nios2-elf-objcopy --input-target srec --output-target ihex "D:\projects\xyz\DE2-115\Onboard_UART_Test\flash\sw.flash" "D:\projects\xyz\DE2-115\Onboard_UART_Test\flash\sw.hex" I then generate the JIC file: I add the Cyclone 4 EP4Ce115 as the flash loader I added the .sof file from quartus as the SOF Data - I use properties to select compression on the SOF file I then add the hex file produced from the command line above - In this window I choose relative addressing and select the hex file Below is a screen shot of my JIC creation window. The JIC creates with no problems. https://www.alteraforum.com/forum/attachment.php?attachmentid=9481 After this I open up the programmer shown below: https://www.alteraforum.com/forum/attachment.php?attachmentid=9482 This seems to go well too. I find the FPGA and attach the EPCS64 configuration flash to it. I then add the JIC file, check the program/configure box and it programs. My nios and Qsys system screen shots below show how I connected/configured all of that. https://www.alteraforum.com/forum/attachment.php?attachmentid=9483 EPCS Controller settings https://www.alteraforum.com/forum/attachment.php?attachmentid=9484 NIOS II Settings - continued on next post b/c of JPG limit
--- Quote Start --- I've still got a problem ... for some reason I can't bootload the nios code. --- Quote End --- To debug this issue, start off by simplifying things, so that you can isolate the issue. For example, does the FPGA load correctly? You could add a JTAG-to-Avalon-MM bridge to your design to confirm that the design is correctly loading from EPCS. Once you have confirmed that, you will know for sure that the issue is related to the NIOS II processor not booting. I don't use NIOS II, so cannot offer much help. If I did, the first thing I would confirm is that it works in simulation. Cheers, Dave
NIOS II Settingshttps://www.alteraforum.com/forum/attachment.php?attachmentid=9485 Now, I've also changed the AS pins discussed two posts up to general IO and connected them to the respective AS pins dclk, data0 etc... https://www.alteraforum.com/forum/attachment.php?attachmentid=9486 When I program the jic file after all this the leds connected to my IO ports all go off completely where as when there is no hardware profile, or the LEDs I don't have connected to anything stay dim so I think the hardware profile is loading. When I power cycle and try to program the nios c code into it though the Nios Eclipse SBTs say that it can't see the target. Pic below https://www.alteraforum.com/forum/attachment.php?attachmentid=9487 So far I haven't been able to get past this. If I changes the nios ii reset vector from EPCS controller to the on chip ram it gets farther, but fails out with a "failed to load elf" error. My system: DE2-115 board Nios II e EPCS controller is connected to nios ii data and instruction bus I've also tried the Flash program in the Nios II eclipse IDE. I start by programming my sof file into the fpga so it has a connection to the EPCS64 device through my Qsys EPCS controller. I then add the sof and elf files to the GUI. https://www.alteraforum.com/forum/attachment.php?attachmentid=9488 It says "No EPCS layout data -looking for section [EPCS-010216]" I'm thinking this means it can't see the EPCS device? So something like the EPCS controller may not be working correctly? Everything I can find on the forum ponts towards it being the AS pins NOT being set to regular IO pins, but I've done that. Any ideas?
Ok sounds good. I'll get on that. Are you saying I should get a .pof file working basically? Load through AS via the Quartus II programmer?
--- Quote Start --- Ok sounds good. I'll get on that. Are you saying I should get a .pof file working basically? Load through AS via the Quartus II programmer? --- Quote End --- Yes. Your NIOS II core can still be in the design, but if you add a JTAG bridge, then you can use system console to access your design. This would then confirm that booting NIOS II is the problem, rather than the image generation for the EPCS device. Cheers, Dave
--- Quote Start --- I do have a question. --- Quote End --- Sorry, I don't use NIOS II tools, so cannot answer this one. However, I'm pretty sure when you set the reset vector to the EPCS, you are not actually running code out of the EPCS, but out of FPGA RAM that is part of the EPCS bootloader/controller. Note that *ALL* of your booting questions can be answered by yourself by simulating the NIOS II processor design in Modelsim :) Cheers, Dave
Great Idea. I'm actually very uneducated regarding simulating nios stuff so I need to delve into that very soon. Thanks for the time I really appreciate it!