Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12603 Discussions

DTG - device tree generator limitations

Altera_Forum
Honored Contributor II
‎03-13-2017 06:39 AM
1,318 Views

Hello, 

 

In documentation it is said: 

 

"There are a number of components that can be connected to HPS portion of the soc (https://rocketboards.org/foswiki/view/documentation/soc) FPGA that require Device Tree information for their drivers. Since Qsys not aware of the components outside the FPGA fabric, this information must be provided to the Device Tree Generator." 

 

I am not sure I understand this, what exactly should be manually added to dts file ? 

 

Can anyone help understanding DTG limitations with dts ? 

 

Regards, 

Ran
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.