Hi,I am trying to access the HPS SDRAM, i.e. DDR3, from the FPGA portion of my Cyclone V chip on the Terasic D0-Nano-SoC devkit. My goal is the following: I have a DMA-capable custom Avalon-MM IP, i.e. a master, that attempts to access a frame stored in the HPS SDRAM. I tested this IP with an on-chip memory without any troubles. Configuration 1 =========== In QSys, I instantiated an HPS with a 32-bit FPGA-to-HPS SDRAM Avalon-MM Read-Only Interface. I generated the preloader using the standard procedure. I have a dummy Linux driver that basically initializes my IP so that it starts reading the HPS SDRAM. However, my IP stalled in this situation (I suspect due to waitrequest being high). The Linux running on the HPS on the other hand was working. Configuration 2 =========== After hours (not to say days :p) of desperate search, I applied the procedure described in this post to my u-boot script: http://www.alteraforum.com/forum/showthread.php?t=51200. Now, it seems that the transfer always starts but once in a while it makes the Linux stalls one time out of two. This is really surprising to me since my custom IP is read-only and therefore shouldn't corrupt the kernel memory. So here are my questions: * Did someone managed to make it work without using desperate solutions as in configuration 2? * Any idea of what I might be doing wrong otherwise? Thank you in advance ! Phil.
Well, the first thing I can think of is that you should try adjusting the weights of the FPGA ports to see if that helps. Other than that, do you know how hard your custom IP is hitting the bus and whether or not you're flooding the SDRAM controller?I've been able to do DDR to SDRAM, but definitely can get stalls if I'm pushing it a bit hard. I'm attempting to mitigate that with better interrupt interrupt handling, etc, but this sounds like something else. This sounds like it might even be some sort of spinlock issue. Does your IP work from userspace? I develop using /dev/mem mappings to start with before hitting the kernel, but that's personal preference.