Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
859 Views

Data Exchange between FPGA and NIOS2

Hi Everyone,  

I want to implement data exchange between NIOS2 and FPGA . For exampe, transfer data form NIOS2 to FPGA with a Dual Port RAM. Is it possible to do that ? 

and how to make that happen? I am waitting for idea, thank U! 

 

NIOS2 (ram1)<--> FPGA(on chip ram2)
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
32 Views

Yes, you can use something simple like a dual port ram and use an interrupt or something when data is available. You would export the 2nd ram port in qsys out to the top level. Or, you can make custom components with avalon bus interfaces.

Altera_Forum
Honored Contributor I
32 Views

Thanks for all your reply! 

 

It Works and finally get this done ! It turns out to be right  

 

I use a dual port ram in NIOS2 and connect port s1 to NIOS2 CPU , port s2 is exported to FPGA top level entity. I am now wondering how to read and write to port S2 in fpga.  

 

below is my Qsys file and top level entity in FPGA project 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8833 https://www.alteraforum.com/forum/attachment.php?attachmentid=8834
Altera_Forum
Honored Contributor I
32 Views

Hi wangyue2725, 

 

did you solve it? 

I am working on the same topic. 

I set up a dual port ram block in qsys with the 2nd slave port exported. i wanted to connect this port to a vhdl module. For testing i connected the address and readdata lines.  

Since a read happens every clock cycle without explicitly enable;  

i thought i could write in C directly to the baseaddress of the dpram and directly read this value from my custom vhdl module. 

in order to do so i assigned from the vhdl module the baseaddress to the dpram and read the value, hoping at one point i would see the value written from the c program.  

But this approach does not work. 

Could you help me with this issue or tell me how you connected your component to the second slave port ? 

 

Cheers 

Tim
Altera_Forum
Honored Contributor I
32 Views

did you see the picture I posted in my above reply? 

when you export the 's2' port to my nios II qsys top level, you will get  

 

 

.dpram_s2_address(exchange_addr), // dpram_s2.address 

.dpram_clk2_clk(CLK_100M), // dpram_clk2.clk 

.dpram_s2_chipselect(1'b1), // .chipselect 

.dpram_s2_clken(1'b1), // .clken 

.dpram_s2_readdata(exchange_rdata), // .readdata 

.dpram_s2_write(exchange_wren), // .write 

.dpram_s2_writedata(exchange_wdata), // .writedata 

 

then you can write or read directly to the Dual Port RAM no other timing logic needed , only pay attention that 'exchagne_wren' must be set to 1'b1 when write data is needed. 'chipselect' and 'clken' must also be set with 1'b1. 

keep contact with me if there is futher problem with this issue. good luck!
Altera_Forum
Honored Contributor I
32 Views

Hey, 

 

yes i did the same than you, but i did not set the clken bit to one. That solved my problem !!! Now i can r/w to memory from VHDL and NIOS/C !! 

Thanks for the advice
Reply