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Debug cannot enter main function when target is DDR

Altera_Forum
Honored Contributor I
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Dear all, 

 

I have some questions about the U-boot. The hardware board is designed by myself. The SoC is 10AS016E4F27E3SG. 

 

I run the Bootloader on the board and print the following information: 

 

U-Boot 2014.10 (May 25 2018 - 14:37:47) 

 

 

CPU : Altera SOCFPGA Arria 10 Platform 

BOARD : Altera SOCFPGA Arria 10 Dev Kit 

I2C: ready 

DRAM: WARNING: Caches not enabled 

SOCFPGA DWMMC: 0 

FPGA: writing socfpga.rbf ... 

Full Configuration Succeeded. 

DDRCAL: Success 

INFO : Skip relocation as SDRAM is non secure memory 

Reserving 2048 Bytes for IRQ stack at: ffe386e8 

DRAM : 1 GiB 

WARNING: Caches not enabled 

 

Can I think that the DDR hardware circuit is correct? Debug can enter main function when target is onchip-ram but debug cannot enter main function when target is DDR,what should i do?
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