Debugging of the FPGA portion using the HPS ARMs & Linux

[Altera_Forum]

Hello All,  

  I have three SPI cores instantiated in the FPGA portion and connected to the AXI3 Lightweight Bridge (ArriaV SX device).    I need to start debugging them (write to SPI cores, read data from them, etc).   What's the simplest way to do so? The ARMs in the HPS portion are able to run linux.    Is it possible to write linux scripts instead of writing C-programs and compiling them to ARM? Are there examples for such scripts?   If writing the C-programs and then letting to ARM run them is the only way to debug FPGA portion, where could I find some simple examples for such programs?     What the simplest and fastest way to start debugging of the FPGA portion using ARMs and linux running in the HPS portion?  What command should I use in order to "open bridges"?    Thank you!

[Altera_Forum]

hps is quite independent, and the debug usually depend on their own tool say ds-5. and to debug fpga for nios, you need eclipse-nios tool. usually to debug nios, we do not invlve the hps arm.

[Altera_Forum]

No, I don't have Nios instantiated in FPGA. But, I have other IPs in the FPGA portion, which are connected to AXI3 Lightweight Bridge. So, in order to operate these IPs, I need to initiate some transactions in the AXI3 Lightweight Bridge, which is connected to ARM.

[Altera_Forum]

hi,, adaptive debugging mode? 

 https://www.youtube.com/watch?v=2nbcuv2txbi

[Altera_Forum]

Thanks! But it's very short video - just about 7 minutes... Thank you anyway!

[Altera_Forum]

I'm confused as to what you're trying to debug. If it is custom SPI code, then you'd need SignalTap or a simulator, and use SignalTap triggering the HPS to halt on a trigger event. 

 If it is the Altera SPI block, then there is a kernel driver available that instantiates the Altera SPI module on the AXI bus as a spidev device, and the HPS can interface directly using the Linux spidev features.  What is your goal?

[Altera_Forum]

The goal is to debug the path from MPU to Altera SPI Core through AXI3 Lightweight bridge.  

 The Linux is not compiled yet... So, I only have the U-Boot and SignalTap-II for debugging the path...  What are suggestions? What's the best way to debug this path?

[Altera_Forum]

--- Quote Start ---  The goal is to debug the path from MPU to Altera SPI Core through AXI3 Lightweight bridge.   The Linux is not compiled yet... So, I only have the U-Boot and SignalTap-II for debugging the path...  What are suggestions? What's the best way to debug this path?  --- Quote End ---    Check out page 7: www.alteraforum.com/forum/newreply.php?do=newreply&p=210842  I suppose you could write some basic bare metal code: http://www.alteraforum.com/forum/showthread.php?t=47099 and then load in your Qsys register map to DS-5 and write bare commands. There are a few different options. On the other hand, why not just get Linux up as well?  As a warning, make sure that you do NOT read or write to memory spaces that don't exist if using Linux. Those drivers aren't very robust for such issues.