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Altera_Forum
Honored Contributor I
1,106 Views

Defparam error in modelsim simulation

Hi, 

I am simulating my project containing a NIOSII, 2 DDR3, QDRII, and other blocs but when I want to simulate on modelsim I have this error and I don't know how to solve it.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_tck.v(201): Invalid reference 'depth' in defparam; target resolves below VHDL scope 'the_altera_std_synchronizer'.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_tck.v(201): Illegal target for defparam.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_tck.v(212): Invalid reference 'depth' in defparam; target resolves below VHDL scope 'the_altera_std_synchronizer1'.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_tck.v(212): Illegal target for defparam.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_sysclk.v(97): Invalid reference 'depth' in defparam; target resolves below VHDL scope 'the_altera_std_synchronizer2'.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_sysclk.v(97): Illegal target for defparam.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_sysclk.v(108): Invalid reference 'depth' in defparam; target resolves below VHDL scope 'the_altera_std_synchronizer3'.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_sequencer_cpu_jtag_debug_module_sysclk.v(108): Illegal target for defparam.# ** Error: /home/to101401/Graphics_newMAIN/ddr3_1_addr_cmd_pads.v(107): Illegal target for defparam. 

 

Any help will be apreciated. 

Thank you
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Altera_Forum
Honored Contributor I
169 Views

I forgot to notice that I am using StratixIV chip and modelsim 6.6c.

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