Hi,I am currently working on a project in which I am interfacing the ANT transceiver (AP2) to the Altera DE2 board through SPI.The ANT transceiver is the master SPI and altera FPGA is the slave SPI. The problem I am currently facing is that, whenever the ANT (master SPI) transmits a byte to the FPGA (slave SPI) on reset, it does not get received in the rxbuffer of the slave in the ongoing iteration. Although, the byte transferred can be seen on the Logic Analyzer. When the ANT is forced to send another byte by resetting it in the next iteration, this time the byte gets received in the slave rxbuffer. Can anyone please help me understand why is this happening? Also, what should I be doing to get rid of this delay and be able to read the byte in the slave rxbuffer as soon as the transaction happens?
Hello,Thanks for the reply! Actually I solved the issue. I figured out that in the slave SPI of NiosII, the slave select line always has to go high in order to store a byte in the rxbuffer. Initially I had grounded it so that the slave SPI is always selected . But in that configuration the slave SPI didn't reset itself and ignored the MOSI byte. So now after I pull the slave select line low, I pull it high after a delay in order to receive the byte on MOSI line.