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Altera_Forum
Honored Contributor I
1,046 Views

Design tree QIP->SDC is not present at the 'Files' tab of my new project

Hi there, 

 

 

I'm making simple experiments with the Nios2 with a cheap CycloneII-based development board by making few changes in demo projects, which came at the CD, and so far there were no issues. These projects were made in quartus 9, and once I'm using quartus 13, I had to convert the original SOPC design to QSYS, also with no problem. 

 

Thereafter, in order to learn in details all steps of the tool I decided to start a new design from scratch, and the things seemed work fine at almost all stages, except when trying to upload the compiled code to board at Eclipse; The following 2 errors apeared everytime, and although I've following several tips recomended here and elsewhere on the web, nothing fixed it: 

 

 

--- Quote Start ---  

-Connected system ID hash not found on target at expected base address. 

-Connected system timestamp not found on target at expected base address. 

 

--- Quote End ---  

 

 

However, comparing my own design with some of the various demo designs which came at the CD, I've noticed that the qip->sdc tree files are present in a hierarchy at the files tab at their designs, but not in mine. Even manually adding my qip file to that tab, the subsequent sdc file were not automatically linked after re-compiling the design in Quartus2. 

 

I also searched on ALTERA's documentations, but unfortunatelly could not find anything explicitly mentioning that.  

The closest reference was the following, but I don't believe it is related to my problem:  

 

 

 

 

Could someone give some tips ?
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5 Replies
Altera_Forum
Honored Contributor I
54 Views

I don't think the order files are listed in your qip file matters. The error messages you show are related to the system ID component. This component is used to match up software with hardware. The error message is caused because you either don't have a system ID component, or you didn't re-generate your hardware definition and BSP in the software build tool after changing your FPGA code. See the software documentation for details on how this all works.

Altera_Forum
Honored Contributor I
54 Views

 

--- Quote Start ---  

The error message is caused because you either don't have a system ID component, or you didn't re-generate your hardware definition and BSP in the software build tool after changing your FPGA code 

--- Quote End ---  

 

 

In regard to regenerate the BSP, I did it many times, as well as I also completely created new BSP designs in order to avoid interference from previous files, but didn't work so far. However, concerning to the "system ID component", I was not aware that it is required. I didn't see it stamped at anyone of the demo examples which came with the kit, but it's nice to know that. At least now I can see at the Nios2 Eclipse "Run configurations" panel something there ( before that, all fields appeared as "Not Found" ): 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=12025  

 

In fact, the ID mentioned above matches exactly to the value configured at Qsys: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=12026  

 

But I cannot understand why it warns that is unconnected, when as we can see, all "nets" are routed : 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=12027  

 

Do you know it there are more details which I could check/configure ? 

 

 

Thanks.
Altera_Forum
Honored Contributor I
54 Views

The system ID component wasn't required in old Quartus versions (8 or 9 perhaps?) from when the Cyclone II came out. Thus you won't find it in older examples. It is possible to tell Eclipse to ignore them, but that would be masking the problem and invite in other bugs as your develop your project. You need to totally delete the directory with the BSP files. Deleting the BSP project in eclipse isn't enough.

Altera_Forum
Honored Contributor I
54 Views

Thank you, but I'm still struggling with that problem without becoming succeed whatever the attempts I have made. 

 

I'm sure that the chip is working fine, due to I can upload to the board via the Jtag cable all binaries already compiled by the kit vendor at an older Quartus2's version, however all projects containing a Nios2 core which I converted from SOPC to QSYS, exhibit the same problem of connected "ID hash" and "timestamp" not found. 

 

I'm realizing: Should it be some Bug related to the conversion SOPC>QSYS performed ?
Altera_Forum
Honored Contributor I
54 Views

Regarding to the issue "missed qip->sdc tree at design" I found the root of the problem. 

I was inserting an empty bloc having the same name than the current Nios2 design wrote in Qsys. 

This also explains the error of "connected id hash and timestamp not found", of course, due there was no core there. 

 

By the way, once I now made the things correctly, Quartus compiled the entire design, but unfortunatelly the amount of 30 MK4 resourses required to synthesize the design could not fit into my modest core ( EP2C5T144C8 ), which has only 26 MK4 , so it's clear that it is time to either upgrade my chip, or purchase a better development kit. 

 

So, I can say that somehow the original problem, as stated, is solved.
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