Design works with NIOS II/e, not II/f

[Altera_Forum]

I have a design in whch I read ADC samples from PIO 

with a dual clock FIFO input and transport the output data with SGDMA to on-chip memory. It took me a few days of experimenting to discover that the reason that it did not work was due to the use of NIOS II/f in stead of NIOS II/e.  Without providing all the details: any idea why NIOS II/f does not work in this case? I would like to use the more speedy II/f.  Thanks, Jos

[Altera_Forum]

Hello Jos, 

 One possible cause for this is DATA CACHE. Search for this on google and you would be able to find some good information regarding this. As a quick check, reduce DATA CACHE memory to 0 when you configure Nios II/f in your Qsys system.  Warm Regards, Bhaumik

[Altera_Forum]

What do you mean with 'not working' ? 

Your design runs but you don't get the expected results or do you mean you can not run the code at all?  In the second case, please note that while Nios II/e is offered free of charge, Nios II/f requires a license. If you don't have one, you must run the design with the USBblaster connected, otherwise the Nios II/f would stop working.

[Altera_Forum]

Hi Bhaumik, 

 Thanks for your suggestion. I will try it and report the result.  Best regards, Jos

[Altera_Forum]

I am sorry for being not more specific. In this case I meant that 

I did not get the expected results. I got constant values in stead of noisy ADC values.  I ran the design with the USBblaster connected, so that was o.k.