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Difference between SDRAM and UDP Packet Data

Altera_Forum
Honored Contributor I
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https://alteraforum.com/forum/attachment.php?attachmentid=15369&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15370&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15371&stc=1 Hello, I'm YJ from Korea. 

 

I developed a data acquisition system with Gigabit Ethernet communication environment. 

 

 

However, when the system transferred data from FPGA to PC, the data at SDRAM and UDP packet is not matched. 

(I checked the SDRAM data at Eclipse Debugging mode, and the packet data with Wireshark. The packet size is 1324 byte, and the data is 1280 byte) 

 

 

As the picture 1(left is packet data, right is memory monitoring) shows, the first packet has data at only first 32 byte, however, the memory has different values at the same location. 

 

The picture 2 shows, the second packet has same data with the value of the memory at yellow shaded area, but the data in red box area are same with the red box of picture 1... 

 

The picture 3 shows same pattern as well. (Green box) 

 

I cannot find a reason why this problem happens.. 

Here is my code.. 

I'm looking forward to your comments on this... 

 

Sincerely, 

 

YJ 

 

volatile int * ActualData = (int *) 0x07000000; *(ActualData+0) = 0xEA380000; // 38-EA-A7-8C-15-34 *(ActualData+1) = 0x34158CA7; // *(ActualData+3) = 0x00080000; *(ActualData+4) = 0x1C050045;// total length 16 (1308)/ type of service 8 / header length 4 / version 4 *(ActualData+5) = 0x00000000;// fragment offset 13 / flags 3 / identification 16 *(ActualData+6) = 0xAAAA1100;// header checksum 16 / protocal 8 / time to live 8 *(ActualData+7) = 0x0500A8C0;// source internet address 32 *(ActualData+8) = 0xADB198A3;// destination internet address 32 //163.152.177.172 *(ActualData+9) = 0x00040004;// source port 16 / destination port 16 *(ActualData+10) = 0x00000805;// checksum 16/ length 16 / 1288 1280 int init=0; for (init =11;init<331;init++) *(ActualData+init) = 0x00000000; int adc =0; int preadc =0x10101010; while (1) { int i=0; for (i=11;i<91;) { //20180322 int j=0; IOWR(0x0800a4a0,0,0x10); for (j=0;j<4;) { IOWR(0x0800a4a0,0,0x11); delay(1); // Read the Packet data starts from X+ adc = IORD_32DIRECT(GPIO_0_BASE, 0); if (preadc != adc) { *(ActualData+(11+(i-11)*4+j))=adc; j++; IOWR(0x0800a4a0,0,0x10); } preadc = adc; IOWR(0x0800a4a0,0,0x12); } i++; IOWR(0x0800a4a0,0,0x04); } IOWR(0x0800a4a0,0,0x06); alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, ActualData, 1324, 0, 1, 1, 0 ); IOWR(0x0800a4a0,0,0x08); IOWR_ALTERA_AVALON_SGDMA_CONTROL (sgdma_tx_dev, 0); IOWR_ALTERA_AVALON_SGDMA_STATUS (sgdma_tx_dev, 0xFF); // Set up non-blocking transfer of sgdma transmit descriptor alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor ); // Wait until transmit descriptor transfer is complete // while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0); delay(10); //10000-> 1us &#51221;&#46020; } return 0; }
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