HiI have a TCP/IP stack running on my NIOS. The big part of the data goes directly from the FPGA-HW to a DDR3 memory, the stack has only to add some addresses etc. Is it somehow possible to forbid caching of some variables? It is just too slow if I have to flush my whole dcache before every DMA-transfer. Thanks for any help
You shouldn't be flushing the entire dcache before doing DMA. There are routines that I have forgotten the name of that will flush only a given area. I don't recommend setting your DMA buffers to be uncached as that will slow down CPU access to that area. After doing a DMA read, invalidate the buffer. Before doing a DMA write, flush the buffer.