08-26-2013 01:59 PM
Hi,With some help from this forum, I've managed to get my project working well. The fpga reads samples from an ADC and enables a flag when the buffer is full. The nios2 polls the edge capture register, then when it sees the flag it reads the data, writes it to SDRAM, resets the edge capture register and repeats until it has read as much data as it wants. This seems to work perfectly, but every now and again it misses some samples from the ADC, all in one block. It's a block of about 20 samples in every 1200, not disastrous but enough to be a nuisance. I assume the processor is periodically doing something else, so my polling loop is too slow. Does anyone know what else the processor could be doing and how I could stop it? I've tried disabling interrupts with alt_irq_disable_all() to no avail. Any other ideas? Thanks Bert
08-27-2013 01:02 PM
How big is your buffer? If the CPU is slow sometimes to react to the edge, you could generate it when your buffer is almost full, so that you have a bit of margin.What happens to your buffer is a new ADC value comes just while the CPU is reading the data? Is this case handled by your hardware and software?