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Altera_Forum
Honored Contributor I
1,398 Views

Do the DMA controller parameters in Qsys all function properly?

I need help with how to correctly set up the dma controller in order to get the maximum data speed between onchip to SDRAM. The current goal is to transmit 60MBytes/sec. I've tried setting the burst transactions and the fifo depth but it seems either I'm doing something wrong or they don't function properly. If anyone can please guide me with a tutorial or steps to take when setting the parameters for the controller that would be great.  

 

I was able to set bytes to send at 128 in my c program and had set Qsys Burst Transactions at 32 and Fifo Depth at 64. With these settings I was only able to send at a rate of 2MBytes/sec from onchip memory to SDRAM. Please let me know of ways to be able to transmit quicker. 

 

Thank you
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11 Replies
Altera_Forum
Honored Contributor I
79 Views

How fast is your system frequency?

Altera_Forum
Honored Contributor I
79 Views

 

--- Quote Start ---  

How fast is your system frequency? 

--- Quote End ---  

 

 

System frequency is 50 MHz
Altera_Forum
Honored Contributor I
79 Views

I am not very familiar with Nios-DMA designs. So do be patient with me. 

 

How is the connection between the onchip-memory-DMA-SDRAM? Is there any sharing of onchip memory/SDRAM with Nios? 

 

You can try to signal tap and see whether transactions at the onchip/SDRAM interface is ok, ie continuous transfer or back-pressure at the interface and root cause the back-pressure. Can you increase the size of the bytes sent? Just to get better average compared to smaller data bytes that can be highly affected by overhead. 

 

How did you come up with the 2MB/sec? Do you have timer/performance counter?
Altera_Forum
Honored Contributor I
79 Views

I agree that you should use signaltap to check what is going on. It's also a very good method to check whether the changes you make to the system has any impact. 

But with such a low bandwidth I don't think that changing the FIFO depth or burst transaction size will do any good. It looks more like a software problem. How much do you keep the DMA busy? If you set it up to go very fast but have a lot of software processing between two DMA transfers then the result bandwidth will be quite low. How big are the memory blocks you transfer from one memory to the other? 

Is the onchip ram accessed from another place at the same time? In that case it can be a good idea to make it dual port and use a port exclusively with the DMA.
Altera_Forum
Honored Contributor I
79 Views

Thanks for the response, I 've been trying a different approach from the hps side but still no luck and that's why I haven't been able to reply sooner. 

 

I've attached an image displaying how sdram controller, dma controller, and onchip are interfaced. I have both the onchip memory and sdram connected to the data master of the nios. When I try to increase the number of bytes to be transferred, I start getting incorrect bytes when reading back the data to verify. This is my biggest issue because I need to be able to write to the sdram at a min of 32MB/sec.  

 

I'll have to look into using signal tap because I've never used it. 

 

I use the alt_nticks(), maybe I need to be using something else? 

 

 

--- Quote Start ---  

I am not very familiar with Nios-DMA designs. So do be patient with me. 

 

How is the connection between the onchip-memory-DMA-SDRAM? Is there any sharing of onchip memory/SDRAM with Nios? 

 

You can try to signal tap and see whether transactions at the onchip/SDRAM interface is ok, ie continuous transfer or back-pressure at the interface and root cause the back-pressure. Can you increase the size of the bytes sent? Just to get better average compared to smaller data bytes that can be highly affected by overhead. 

 

How did you come up with the 2MB/sec? Do you have timer/performance counter? 

--- Quote End ---  

Altera_Forum
Honored Contributor I
79 Views

What do you mean by setting it up to go very fast? The goal is to be able to write to the entire sdram using dma. Right now, I'm only transmitting 256 bytes from on-chip to sdram, but that's in a loop to test for transmitting 4MB and even with that I'm getting incorrect bytes when reading the sdram. 

 

 

--- Quote Start ---  

I agree that you should use signaltap to check what is going on. It's also a very good method to check whether the changes you make to the system has any impact. 

But with such a low bandwidth I don't think that changing the FIFO depth or burst transaction size will do any good. It looks more like a software problem. How much do you keep the DMA busy? If you set it up to go very fast but have a lot of software processing between two DMA transfers then the result bandwidth will be quite low. How big are the memory blocks you transfer from one memory to the other? 

Is the onchip ram accessed from another place at the same time? In that case it can be a good idea to make it dual port and use a port exclusively with the DMA. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
79 Views

It depends on how you use alt_nticks. It's perfectly ok if you use it to count the bandwidth over a high number of ticks, but if you just use it to count how many bytes were sent between two ticks you'll get unreliable results. 

Is the bandwidth increasing where you use larger blocks? 

 

As for the incorrect bytes read back, does your Nios CPU have a data cache? If yes did you remember to invalidate the area you check, or to bypass the cache when reading the data back?
Altera_Forum
Honored Contributor I
79 Views

Yes, the bandwidth does increase as I increase data blocks, so I don't believe that's the issue. I ran a test of transmitting 128 bytes in a loop of 100000 and got 2.56 MBytes/sec. Shouldn't I be getting much better results with the DMA? I recall looking at a different thread and I believe someone was getting a throughput of over 100 MBytes/sec! 

 

I'm still verifying the incorrect data bytes but no I do not have data cache on my Nios. 

 

 

--- Quote Start ---  

It depends on how you use alt_nticks. It's perfectly ok if you use it to count the bandwidth over a high number of ticks, but if you just use it to count how many bytes were sent between two ticks you'll get unreliable results. 

Is the bandwidth increasing where you use larger blocks? 

 

As for the incorrect bytes read back, does your Nios CPU have a data cache? If yes did you remember to invalidate the area you check, or to bypass the cache when reading the data back? 

--- Quote End ---  

Altera_Forum
Honored Contributor I
79 Views

Should I be setting the DMA parameters to certain values in Qsys to get the maximum throughput?

Altera_Forum
Honored Contributor I
79 Views

I think you need to connect a Signaltap instance to the DMA to see what is happening. It won't be possible to guess what is happening and what the problem is without checking those signals.

Altera_Forum
Honored Contributor I
79 Views

You could probably try on simulation?

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