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DKolo
Novice
1,311 Views

Does app note AN706 apply to Arria10SoC?

Are you able to map an HPS IP Peripheral Signals to the

FPGA fabric, such as a UART controller?

 

In the case of Arria10SX Dev Kit, routing the DB9 RS232 port (of the FPGA fabric) to the HPS uart controller. (in addition to the usb-to-uart port connected to the HPS; requiring a 2nd uart)

 

Seems I am able to choose if the signals are coming from FPGA or HPS dedicated/shared IOs in Platform designer --> HPS --> Pin Mux and Peripherals Tab.

But found a similar post which is implying this is not possible for A10SoC and requires an fpga-hps bridge with corresponding IPs in the FPGA fabric.

https://forums.intel.com/s/question/0D50P00003yyGafSAE/routing-hps-gpio-to-an-led-in-fpga-region?lan...

 

Some clarification would be appreciated.

 

2 Replies
Fawaz_J_Intel
Employee
100 Views

Hello sir,

Let me check on this with our internal team.

I will come back to you soon,

 

 

Thanks

Fawaz_J_Intel
Employee
100 Views

I think it is possible.

A10 devkit user guide mentions below.

u.jpg

 

 

However, HPS debug port connection depends on boot device. UART in NAND device connects to Shared I/O. UART in the other device connect to Dedicated I/O.

If you want to change this behavior, you need to change MAX V design. Please check schematics below.

 

g.jpg

Hope this might help.

 

 

Thanks

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