Hello mates,I read all the threads on the error "downloading ELF process failed". I am designing a basic system using Nios II core with LEDs and switches. I prepared a core and instantiated it in a top level entity. Then I made a .bdf file with switches and LEDs interfaced to it, along with clock and reset. Also, a .sdc file is included before the execution where I followed all the steps given in the timing quest analyser tutorial. I've attached a block diagram of my circuit. In Nios II for eclipse, I am currently trying to execute hello world but that too is not working correctly. It gives the error downloading ELF process failed. I would like to mention that my core is executing perfectly when I instantiate it only in vhdl and use that to execute some program and see the output in Nios II console but it gives errors when I try to include switches and LEDs. Query: 1. When I generate the project, the timing analyser turns red saying unconstrained paths, those are the same amount of pins for my switches and LEDs. How do I remove this problem? I read in few threads that unconstrained paths are because of inclusion of latches in the circuit but I am using just normal switches and LEDs, so that should not be a problem. 2. I also found that I use AG14 pin for clk which is supposed to be 50MHz on-board but the altera_reserved_tck is 10MHz, so if I interface an external clock it is bound to give an error, so do I need to scale down the clock to make it work with the inbuilt altera_reserved_tck or that should not be a problem.? 3. Due to the above circuit modifications, I get a warning that "overwriting existing clock: altera_reserved_tck", what should I change here to make them work in tandem. 4. I also get another while downloading the program and I don't know if it is related to my problem. The nios II console gives an error saying "C:\altera\13.0\nios2eds\bin\gnu\H-i686-mimngw32\bin\nios2-elf-objcopy.exe: 'found' : No such file found.srec unable to open input file. rm: cannot remove `found.srec` : No such file or directory found. thanks a lot.
1. In your case the unconstrained paths warning is not an issue, since switches and LEDs signal are not timing critical and there's usually no point in constraining them. You can simply ignore the warning. If you want to get rid of these warnings you must explicitly tell TimeQuest to ignore those paths or place some fake constraints.2. altera_reserved_tck, as you can guess from the name, is a reserved clock automatically generated by Quartus for special functions. IIRC is used for managing jtag circuitry. This is unrelated to your main 50MHz clock, so you can cut the paths between them 3. This is very strange. Your sdc file should declare a create_clock to define your main clock net. Did you assigned it the name "altera_reserved_tck" ? That's would be wrong since another clock with this name is already implicitly created, as I said above.
Thanks a lot for your reply. I now understand that unconstrained paths are not an issue here. Also, the altera_reserved_clk did not have problem.I was able to create .sdc file and my circuit is working correctly now along with switches, LED and LCD as well. Just one quick question, I followed the steps correctly but I did not use .BDF file while I got the output. When I have .vhd file as my top entity where I instantiate my processor then the circuit works correctly, whereas I get ".ELF download fail" error if I use .bdf as my top level entity. Could you please tell me why that happens? Thank you.
Might have been signals moving around in the symbol. SOPC Builder used to do that a lot but I'm not sure about Qsys since I haven't used schematic entry for a while. To check for that rightclick the background of your schematic and click on "refresh schematic" or whatever it's called (I don't have Quartus installed and I forget what the option is called). That'll update all the symbols in your design in case any of them changed.Also if you didn't already constrain the JTAG I/O I recommend doing so. If you look at any Nios II design example that targets Cyclone III or up there should be a constraints file that has some for the JTAG I/O. It would take a while to explain why they are needed so take my word for it :) The LEDs and pushbuttons are asynchronous so you can cut those paths.
I agree with BadOmen about refreshing the schematic symbol in order to check if all the pins are still in the right places.You can even proceed in the inverse direction and tell Quartus to generate a HDL file from schematic to verify any anomaly. I also suggest to check the reset signal: has it the correct polarity? Once I spent a lot of time with a similar issue before discovering I had a signal named reset_n in the sopc component which I actually had wrongly defined active-high.