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Altera_Forum
Honored Contributor I
1,714 Views

EDS 14.0 tool dtc

So i'm trying to edit my socfpga.dtb file bij using the socfpga.dts file. But with EDS 13.1 you could do "dtc -I dts -O dtb -o socfpga.dtb socfpga.dts". 

Only with EDS 14.0 the command doesn't work anymore. Anybody know how to convert a .DTS to an .DTB
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11 Replies
Altera_Forum
Honored Contributor I
119 Views

I ran into this as well and reverted back to 13.1 tools. I was not successful at the time, but I believe that I found that there was a mode in sopc2dts 

to produce a dtb file -- but I never got it working. I was surprised that I didn't find any info at the time either. 

 

Hopefully someone can comment on that.
Altera_Forum
Honored Contributor I
119 Views

I tried again tonight -- this is the command line i used with the SoCKit -- but it reported some errors. In the end the kernel hung up . Based on some comments I read on the rocketboards list, others have had the problem but I haven't had time to track it down. 

 

(14.0 tool chain) 

sopc2dts --input soc_system.sopcinfo -t dtb --output socfpga.dtb --board soc_system_board_info.xml --board hps_clock_info.xml
Altera_Forum
Honored Contributor I
119 Views

I have the same problem. Thats why i wanted to edit the .DTS file. If you replace "dtb --output socfpga.dtb" bij DTS. You get the DTS file. 

 

 

sopc2dts --input soc_system.sopcinfo -t dts --output socfpga.dts --board soc_system_board_info.xml --board hps_clock_info.xml 

 

You can also rewrite to "sopc2dts -i soc_system.sopcinfo -t dts -o socfpga.dts" 

 

So the Debuf console=ttyAL0, Normaly i would chose "bootargs = "console=ttyS0,115200";" 

chosen { 

bootargs = "debug console=ttyAL0,115200"; 

}; //end chosen 

 

 

Also the memory is not correct i thing. 

 

memory@0 { 

device_type = "memory"; 

reg = < 0xC0000000 0x00010000  

0xFFFF0000 0x00010000  

0x00000000 0x80000000 >; 

}; //end memory@0 

 

 

I have 256 MB , so it has to be (i think). 

 

memory { 

device_type = "memory"; 

reg = <0x0 0x10000000>; 

}; 

 

So the Question = How do you convert a Socfpga.dts to a Socfpga.dtb
Altera_Forum
Honored Contributor I
119 Views

Solved... 

 

So i tried to use DTC (device tree converter) under windows, but i guess this doedn't work well, or i didn't do i right. But under Linux it works fine. I use Ubuntu 12.04LTS. 

 

You can get the converter by typing "sudo apt-get install device-tree-compiler" in the consol of you linux machine. 

 

after that you can use the converter to convert DTS to DTB and visa versa. 

 

 

(Underneath a peace of infor from https://git.kernel.org/cgit/utils/dtc/dtc.git/tree/documentation/manual.txt

 

2) Description 

 

The Device Tree Compiler, dtc, takes as input a device-tree in 

a given format and outputs a device-tree in another format. 

Typically, the input format is "dts", a human readable source 

format, and creates a "dtb", or binary format as output. 

 

The currently supported Input Formats are: 

 

- "dtb": "blob" format. A flattened device-tree block with 

header in one binary blob. 

 

- "dts": "source" format. A text file containing a "source" 

for a device-tree. 

 

- "fs" format. A representation equivalent to the output of 

/proc/device-tree where nodes are directories and 

properties are files. 

 

The currently supported Output Formats are: 

 

- "dtb": "blob" format 

 

- "dts": "source" format 

 

- "asm": assembly language file. A file that can be sourced 

by gas to generate a device-tree "blob". That file can 

then simply be added to your Makefile. Additionally, the 

assembly file exports some symbols that can be used. 

 

 

As far as the Device tree go's. Myn doesn't work either when i creat it with Sopc2dts. 

 

i use the on from http://www.rocketboards.org/foswiki/documentation/gsrd140devicetreegenerator 

You must ofc change the device tree to match your board. 

 

Good luck.
Altera_Forum
Honored Contributor I
119 Views

The dtc command is " dtc -I dts -O dtb -o socfpga.dtb socfpga.dts" you ofc change the name, and switch DTS and DTB ( dtc -I dtb -O dts -o socfpga.dts socfpga.dtb)

Altera_Forum
Honored Contributor I
119 Views

So  

(looks like I was editing my response below while you added in yours). 

 

 

So are you saying that your device tree still doesn't work or that after you installed dtc and used the additional command line options for for the newer "sopc2dts"program it actually worked for you? 

 

thanks! 

-Lance 

 

 

[snip] 

Thanks for your comments. I was thinking that the device tree compiler functionality was replaced, but I guess it is just that dtc doesn't ship with the soceds -- just last night I found I could install it stand-alone (on ubuntu sudo apt-get install device-tree-compiler). 

 

I'm going to run through the whole routine again and see if I can get a working result.
Altera_Forum
Honored Contributor I
119 Views

It isn't clear if yours is working (I haven't gotten that far yet). I did just find some notes from the rocketboards RFI mailing list -- not sure if this is complete but I have to post snippets since links I post get held up in moderation: 

 

These are from some messages posted to that list July 16th, 2014 

 

[snip1] 

In the latest release of the Arrai V SOC Development kit, The file hps_clock_info.xml file is missing. 

In the prior revision, it was necessary for building the device tree of the development board and is 

specified in all the documentation. Without it, the socfpga.dtb created doesn't allow linux to boot 

completely. Also, there is a new file hps_common_board_info.xml. Should this be used in addition 

to ghrd_5astfd5k3_board_info.xml. 

 

Please advise, 

[end snip1] 

 

[snip2] 

 

look at the makefile in the 14.0 example design. the sopc2dts call adds a 

--clocks parameter that causes sopc2dts to add the clock info provided in 

14.0 generated qsys sopcinfo files. you dont need a clock xml any longer. 

[end snip2]
Altera_Forum
Honored Contributor I
119 Views

Thnx for the info. i've got linux running. 

 

I generated the socfpga.dts with the following command 

 

sopc2dts --input ghrd_5astfd5k3.sopcinfo 

--output socfpga.dtb 

--type dtb 

--bridge-removal all 

--clocks 

 

I didn't use the XML files. But you need to edit the socfpga.dts file a little to get it working. 

 

i changed the first part to  

 

model = "Altera SOCFPGA Cyclone V"; 

compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 

# address-cells = <0x1>; 

# size-cells = <0x1>; 

 

aliases { 

ethernet0 = "/sopc/ethernet@0xff700000"; 

}; 

 

 

cpus { 

# address-cells = <0x1>; 

# size-cells = <0x0>; 

 

cpu@0x0 { 

device_type = "cpu"; 

compatible = "arm,cortex-a9-14.0", "arm,cortex-a9"; 

reg = <0x0>; 

next-level-cache = <0x1>; 

}; 

 

cpu@0x1 { 

device_type = "cpu"; 

compatible = "arm,cortex-a9-14.0", "arm,cortex-a9"; 

reg = <0x1>; 

next-level-cache = <0x1>; 

}; 

}; 

 

 

So another thing i changed to get it running is the EMAC.  

 

ethernet@ff700000 {  

+ phy-mode = "rgmii"; 

 

 

After those two things I got Linux running.
Altera_Forum
Honored Contributor I
119 Views

That's great, thanks. I got a build that worked but at bootup there were a few warnings about device tree entries. I'm building from scratch again then will go back and take your suggestion at looking at these settings.  

 

If I find anything unique for SoCKit users, I'll try to post it somewhere. 

Lance
Altera_Forum
Honored Contributor I
119 Views

Question - 

Using Linux for hosting the tools. 

 

Has anyone added any custom IP's? I started with the GSRD for the Altera Cyclone V Dev Kit. We added a custom IP and a PLL. I generate a *.dts file that I add the driver information but the PLL isn't in the *.dts because in Quartus14.1/Qsys there is no base address because it is like the other clocks. 

 

So, how do I get the PLL recognized properly for my .dtb file?
Altera_Forum
Honored Contributor I
119 Views

 

--- Quote Start ---  

Question - 

Using Linux for hosting the tools. 

 

Has anyone added any custom IP's? I started with the GSRD for the Altera Cyclone V Dev Kit. We added a custom IP and a PLL. I generate a *.dts file that I add the driver information but the PLL isn't in the *.dts because in Quartus14.1/Qsys there is no base address because it is like the other clocks. 

 

So, how do I get the PLL recognized properly for my .dtb file? 

--- Quote End ---  

 

 

SOLVED -- Using 14.1 tools and a suggestion - 

I took the GSRD *.dtb file used the sopc2dts (NOT IN THE COMMAND SHELL) and made a *.dts file. I added my custom IP and the pll as a fixed clock - like "clk_0" is in the GSRD into that "clocks" section. 

 

pll_0: pll_0 { 

compatible = "fixed-clock";# clock-cells = <0>; 

clock-frequency = <1843198> /* 1.843198 MHz PUT YOUR VALUE HERE */ 

clock-output-names = "pll_0_outclk0"; 

}; //end pll_0 (pll_0) 

 

THEN I GENERATED A *.dtb file using the 14.1 "dtc" 

# ] ./dtc -I dts -O dtb -o socfpga.dtb socfpga-AddedMyIPs.dts 

 

THIS BOOTS so now I need to try my device driver, etc
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