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Altera_Forum
Honored Contributor I
994 Views

EPCS controller clock

Hi, 

 

I have a NIOS2 Qsys design (ARRIA V, Q14.1) with an EPCS flash controller in it to copy the software from the serial FPGA configuration flash into DDR ram memory at power-up. This copy action takes a few seconds. I want to reduce this time as much as possible.  

I measured the serial clock frequency used to read from the serial flash and it is at 15Mhz.  

I already doubled the NIOS CPU clk from 30 to 60Mhz, but the serial clock remains at 15Mhz. 

 

How can I increase the clock frequency used by the EPCS controller so the copy from flash is done faster? 

 

AJV
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4 Replies
Altera_Forum
Honored Contributor I
51 Views

AFAIK the frequency is hardcoded in the controller and can't be changed. But the EPCS controller is nothing more than a SPI controller and a ROM containing the bootloader, so you can instead put your own SPI controller with the frequency you specify, put a custom bootloader in a on-chip ROM block and make the CPU boot from that ROM. 

Read the EPCS datasheet though. With the normal read bytes command the maximum frequency is 20MHz. There is also a fast read command that can operate at up to 40MHz, but I don't know which one the standard bootloader uses.
Altera_Forum
Honored Contributor I
51 Views

The EPCS is connected to the default FPGA configuration pins. These pins are not available as user I/O pins in an ArriaV, so I can't connect my own SPI controller or is there another work-around to connect to these pins??

Altera_Forum
Honored Contributor I
51 Views

There is a work-around. You can add a serial flash loader IP to your design (through the Megawizard) and use the "Share ASMI interface with your design" option. That way you can program your EPCS with the Quartus programmer through JTAG, and access the pins from your design. 

I've never tested it myself but it should work.
Altera_Forum
Honored Contributor I
51 Views

did you try on 15.1, maybe this had been fixed?

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