Hi Everyone,I have a Cyclone IV EP4CE22F17C7N FPGA on the board that I'm working on and I am confused on the whole EPCS/EPCQ/JTAG-UART configuration of the FPGA. On my Qsys system, I have: Nios II Processor On-Chip Memory 2x PIO EPCS_flash When I am using Nios II SBT, I tried programming/configuring the FPGA through Nios II's "Quartus Programmer" with my USB blaster plugged into the JTAG port of my board. I found the .sof file that I had used for my project and programmed the FPGA through Nios II this way. Am I doing this wrong? Am I supposed to use the Active Serial port when I'm programming with EPCS? When I try to switch over the USB Blaster to the Active Serial port to program it that way (in Quartus II), I have to add a device and I don't know which one to choose (EPCSx/EPCQx, x=1,4,16,64,128). Also, do I need to include a JTAG-UART component in my Qsys system? I tried reading all of Altera's documents on JTAG-UART and EPCS/EPCQ and I got confused... Also, when I tried to debug the app (Right click app>Debug As> Nios II Hardware) with the USB blaster plugged in to the JTAG port, I tried to check the system ID properties and for all of the criteria (expected system ID base address, expected system ID, connected system ID, expected system time stamp, and connected system timestamp) everything is listed as "Not Found". I had to check the "Ignore mismatched system ID/timestamp" boxes in the Target Connection tab to get my program to build successfully. Anyways, I hope this makes sense. Thanks for your help. I really appreciate it...
The JTAG interface on the FPGA allows it to be configured (via the .sof) and allows FPGA fabric access after the FPGA is configured, eg., the JTAG-UART.The EPCS configures the FPGA at power-on. Typically you would use JTAG to configure the FPGA while you are debugging a design, and once you are happy with it, you can program the EPCS device. To add to your confusion, EPCS devices can be programmed either using an "Active Serial" header (which your board sounds like it has), or via JTAG in a two step process where Quartus first configures the FPGA with a design containing the Serial Flash Loader (SFL) component (a design containing JTAG-to-FPGA fabric logic), and then Quartus uses that design to program the EPCS device. This is called JTAG indirect configuration and requires you convert the programming file(s) to .jic format. Using JTAG to program the EPCS device involves a couple more steps, but its nicer in that you do not have to keep changing connectors on your board (most new boards do not even bother to include an AS header). Cheers, Dave
Hi Dave,Thanks for the quick response! So, if I want to just configure my FPGA with JTAG, do I have to add a JTAG-UART component to my Qsys system? Thanks!
--- Quote Start --- So, if I want to just configure my FPGA with JTAG, do I have to add a JTAG-UART component to my Qsys system? --- Quote End --- No you do not have to include the JTAG-UART. However, if you are trying to debug your system and the NIOS II IDE is configured to expect the UART, then of course you will need it. Cheers, Dave