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ERROR: tb.dut.master_0.mm_master_vhdl_wrapper.<protected> .<protected>: Illegal c

Altera_Forum
Honored Contributor II
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I've developed a custom Avalon-MM Slave IP component in VHDL and I'm trying to test it in Modelsim. I've based my test bench on the Avalon Verification example, avlmm_1x1_vhdl, which simulates fine, but because I'm simulating a custom slave I don't have a slave_0 Avalon-MM Slave BFM library associated with it so I've modified the test_program.vhd to only send master commands, and removed all Avalon-MM Slave BFM-specific code from test_program_pkg.vhd. 

 

However when I simulate I get the following error: 

 

950: ERROR: tb.dut.master_0.mm_master_vhdl_wrapper.<protected>.<protected>: Illegal command while reset asserted 

 

I haven't changed the reset signal functionality - it's the same as in the avlmm_1x1_vhdl example, and tb/reset is high for a time then gets set low. 

 

Any idea what I could be doing wrong?
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