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Altera_Forum
Honored Contributor I
945 Views

Enable L2 Cache

Hi! 

 

Is there an simple(!) example on using the L2 Cache (using hwlib)? 

 

 

My current test project places some code(some few KB) at 32MB offset (0x0200 0000), so i guess it ends up in DDR Ram. 

 

All alt_cache_* functions are placed in on-chip-ram at 0xFFFF0000. 

 

This is what i do: 

- setup interrupt vector 

- call alt_cache_system_enable 

- assign one variable to another 

 

This is what happens: 

- code runs fine 

- the variable assignment results in wierd behaviour. "step over source line" doesn't work anymore, i guess the cpu just goes wild. 

 

Enabling the L1 Cache without L2 Cache works so far, but thats not even the half story. ;) 

 

I guess i need to setup the MMU bevore calling alt_cache_system_enable. 

 

So i tried the following code. One section that spans 64MB, starting from address 0: 

ALT_MMU_MEM_REGION_t regions; regions= (ALT_MMU_MEM_REGION_t) { .va = 0x00000000, .pa = 0x00000000, .size = 64*1024*1024, .access = ALT_MMU_AP_PRIV_ACCESS, .attributes = ALT_MMU_ATTR_WBA, .shareable = ALT_MMU_TTB_S_NON_SHAREABLE, .execute = ALT_MMU_TTB_XN_DISABLE, .security = ALT_MMU_TTB_NS_SECURE }; uint32_t * ttb1 = NULL; status = alt_mmu_va_space_create(&ttb1, regions, 1, alt_pt_alloc, alt_pt_storage); 

 

no luck there, cpu goes wild in alt_mmu_va_space_create. 

 

any hints/code?
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2 Replies
Altera_Forum
Honored Contributor I
45 Views

Moving to the baremetal section of the forum so that people will actually see your post (avoid posting under SoC directly, nobody will see your post way down there).

Altera_Forum
Honored Contributor I
45 Views

I think I may know the problem that you have. Something similar happened to me too :) 

 

The issue seems to be that you just define the 64MB that you want. This makes the rest of the memory inaccessible. 

Then the Debugger tries to access other memory (or your application tries to access some peripheral that is not defined in the MMU table) and everything blows up. 

 

What you need to do is provide MMU tables for all the memory, describing which areas are cacheable and which not (like peripherals). 

 

Please take a look at the additional HWLIBs examples at http://www.altera.com/support/examples/soc/soc.html.  

 

Specifically get the example called "Quad SPI". Inside you will see a working example on using caches: 

  • Files "alt_pt.c" and "alt_pt.h" contain the MMU tables. 

  • File "qspi_demo.c" contains the function "system_init()" which, among other things, sets up the MMU and caches. 

 

Note that these examples are also accessible by: 

  1. Go to www.altera.com 

  2. Click on "Support" 

  3. Click on "Design Examples" 

  4. Click on "SoC"