Equivalent Avalon functions

[Altera_Forum]

Hello all, 

I am writing a software translation layer and I need to know what the Avalon functions are that equate to Xilinx's FSL I/O functions including   getfslx(val, id, f1ags)  putfslx(val, id, flags) tgetfslx(val, id, flags) tputfslx(id, flags) getdfslx(val, var, flags) putdfslx(val, var, flags)  tgetdfslx(val, var, flags) tputdfslx(var, flags)  Basically, what are the low-level Avalon read/write functions and where are they defined? Any insight would be appreciated, thank you. -Brad

[Altera_Forum]

Try looking in nios2eds/components/altera_nios2/HAL/inc/io.h.

[Altera_Forum]

Comparing Avalon to Xilinx's FSL is kind of incorrect.  

 Xilinx's FSL (fast simplex link) is Xilinx's best attempt at a high throughput path between the Microblaze or PowerPC and custom user logic.   With Altera, you have two options: 1 - Create custom user logic. This would be a peripheral on the Avalon bus. The closest comparison would be a PLB or IPIF peripheral in Xilinx. Although Avalon is significantly faster. In this case the file "io.h" that Kevin pointed you to is the recommended way for accessing the component. If I remember correctly, Xilinx's SDK also gives you a "xio.h" file which basically just provides macros for accessing data. See the section beginning on page 9-4 of the following document: http://www.altera.com/literature/hb/nios2/n2sw_nii52007.pdf  2 - Create a custom instruction. Xilinx's FSL is most similar to this but custom instructions truly offer superior speed and flexibility. http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf  So, if you're just using an avalon component, use the IOWR and IORD macros or you can simply access the component as memory but you most bypass the cache. If it's a custom instruction you are creating, read the user guide I've given above.  Jake

[Altera_Forum]

Jake and Kevin, 

I appreciate the quick and detailed replies.   I understand that FSL and Avalon shouldn't be directly compared, but they were similiar enough such that we were able to create a simple and small hardware translation layer such that a Nios II can talk to FSL peripherals.    I am tasked with creating the software to translate from the Xilinx calls to Avalon peripheral access calls. This seems pretty trivial but I will have to do some translation of addresses since they are certainly not the same for the two processors.    I think IORD and IOWR will end up being the most straightforward for me.   Thanks, -Brad