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Valued Contributor III
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Error (10170): Verilog HDL syntax error at nios_system_inst.v

Hello all, 

 

I got the following error while trying the Introduction to the Altera SOPC Builder 

Using Verilog Design SOPC Tutorial. I'm using Quartus II 10.0 . I'm lost on figuring it out. 

 

Error (10170): Verilog HDL syntax error at nios_system_inst.v(2) near text "("; expecting ";", or "," 

 

Here is the SOPC auto generated code: 

 

//Example instantiation for system 'nios_system' 

nios_system nios_system_inst  

.clk_0 (clk_0), 

.in_port_to_the_Switches (in_port_to_the_Switches), 

.out_port_from_the_LEDs (out_port_from_the_LEDs), 

.reset_n (reset_n) 

); 

 

Can anyone assist please, because I am stumped.  

 

Thanks in advance,
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Valued Contributor III
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I can't see anything wrong with syntax. I am only not sure about where the error is since it says it is located at nios_system_inst.v and this may not mean the code you are showing. I wonder why the file name is same as instant name.

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Valued Contributor III
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the _inst.v is just an example Verilog instance. you'll need to drop it into a module and port map it

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Valued Contributor III
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Thank u for replying me.. 

 

That was not a code written by me. it was generated by the SOPC.I done it according to the tutorial. But it didnt compile......
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Valued Contributor III
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I'm getting the same error as mentioned here. Couldn't find any syntactical error in the code. Moreover, it is a Quartus auto-generated code which is not running in Quartus :confused: :rolleyes:. Please help me compile this.

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Valued Contributor III
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Please do not multipost, it won't get you more answers. 

Regarding the error, as already said in the thread an *_inst.v file is just an instantiation example and shouldn't be compiled as is in a project. Remove the file from the project and copy/paste its contents in a top level file if necessary.
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