Hi there,
I am building a new component in component editor for SOPC builder. I added 2 package files and a design file for the new component, all in VHDL. When it analyzes the files, it reports an error message like below:
Error (10867): Verilog HDL or VHDL XML Interface error at
xxxx.vhd(32): port "
xxxx" has an unsupported type File
:/the path to the design file/ Line: 32.
The line in question is a input signal definition in the entity for the new component, it looks like:
coe_c0_rx_crc_err_cnt_st : in t_lev2_rx_d_32bit_cnt := (others => (others => '0'));
where the t_lev2_rx_d_32bit_cnt is a array type defined in one of the package files, which looks like:
type t_lev2_rx_d_32bit_cnt is array(11 downto 0) of std_logic_vector(31 downto 0);
I can't find out what the error message is about. Could anyone point out the problem here?
Your help will be very much appreciated.
Hua
