Error (204012): Can't generate netlist output files because the file ..

[Altera_Forum]

hello.. 

 i am new in altera. recently i start to develop project with qsys nios ii/s using altera web version. but when i am starting compilation of code it shows error like...  Error (204012): Can't generate netlist output files because the file "...../Nios/synthesis/submodules/Nios_cpu.v" is an OpenCore Plus time-limited file  i searched on google about this error..i also found some solution like, this error related to Altera IP licensing.so i wont be able to generate netlist for this particular file.  and second solution like i need to disable EDA tool from EDA setting.  but my actual question is, it is possible to dump my project file on FPGA with out only this file.  if it is not possible then how get this ip licence.or i need to buy only ip licence or required altera pro version tool.  

[Altera_Forum]

Hi, 

 1.Which type of NIOS II are you using? use Nios II economy and check.   --- Quote Start ---   but my actual question is, it is possible to dump my project file on FPGA with out only this file.  --- Quote End ---   Yes, you can program FPGA with web edition.   --- Quote Start ---   if it is not possible then how get this ip licence.or i need to buy only ip licence or required altera pro version tool.  --- Quote End ---   Regarding Lincence refer below links https://www.altera.com/support/support-resources/support-centers/licensing.html https://www.altera.com/support/support-resources/download/licensing/lic-q2se_licenses.html https://www.altera.com/support/training/demonstrations/online/licensing/onl-licensing.htm.html https://www.altera.com/support/support-resources/download/licensing/overview.html  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

1.which type of nios ii are you using? use nios ii economy and check.  sir i am using nios ii/s.  if this nios_cpu.v is not generating.then how dump this file on FPGA i am not understanding.  will you plz,elaborate the same further.

[Altera_Forum]

The EDA tool is only useful if you need to export the netlist to another tool. To configure the FPGA you just need a sof file, generated by the assembler. You can configure the FPGA with your sof file without license but it will run in Opencore evaluation mode and you need to keep the USB connection with the programmer the whole time. 

Alternatively you can switch to a Nios II/e core that doesn't require a license.

[Altera_Forum]

--- Quote Start ---  The EDA tool is only useful if you need to export the netlist to another tool. To configure the FPGA you just need a sof file, generated by the assembler. You can configure the FPGA with your sof file without license but it will run in Opencore evaluation mode and you need to keep the USB connection with the programmer the whole time. Alternatively you can switch to a Nios II/e core that doesn't require a license.  --- Quote End ---    thank you sir....

[Altera_Forum]

--- Quote Start ---  Hi,  1.Which type of NIOS II are you using? use Nios II economy and check.  Yes, you can program FPGA with web edition.  Regarding Lincence refer below links https://www.altera.com/support/support-resources/support-centers/licensing.html https://www.altera.com/support/support-resources/download/licensing/lic-q2se_licenses.html https://www.altera.com/support/training/demonstrations/online/licensing/onl-licensing.htm.html https://www.altera.com/support/support-resources/download/licensing/overview.html  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---    thank you sir...