Error booting linux on Nios II on Stratix V

[Altera_Forum]

I made the necessary kernel images (as per instructions on : http://www.rocketboards.org/foswiki/documentation/niosiilinuxusermanual#building_u_45boot) 

Now, when I try to nios2-download -g ~/linux-socfpga/vmlinux && nios2-terminal I get the following error :   Using cable "DE5 Standard [2-1.7]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 3523KB in 5.1s (690.7KB/s) Verifying C0000000 ( 0%) Verify failed between address 0xC0000000 and 0xC000FFFF Leaving target processor paused   Is this because my memory is incorrectly configured?  Also,    1. On the page http://www.rocketboards.org/foswiki/documentation/niosiilinuxusermanualforstratixiv Under the section To boot Nios II linux from CFI flash, we make a proper address mapping, programming the u-boot image first (at the CPU base address), then the DTB and then the Linux kernel with built in rootfs.   In the method (To boot Nios II linux from RAM), we do no such thing, neither do we program u-boot nor anything related to rootfs. All it says is that we compile the .dts file into the kernel (in make menuconfig). Is this *all* that is required ?   2. My error says conflict between 0xC0000000 and 0xC000FFFF ; why and how does it reach to 0xC ?    I'd greatly appreciate any help on this.

[Altera_Forum]

Hi, 

   --- Quote Start ---   I get the following error :   Using cable "DE5 Standard [2-1.7]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 3523KB in 5.1s (690.7KB/s) Verifying C0000000 ( 0%) Verify failed between address 0xC0000000 and 0xC000FFFF Leaving target processor paused    --- Quote End ---     The downloader 'nios2-download' will verify whether the downloaded data is correct or not. The error means that the memory contents between address 0xC0000000 and 0xC000FFFF are different from those of your 'vmlinux' file. If you map your main memory from the address 0x00000000, please check the timing of those interface.  About the question 'why and how does it reach to 0xC ?', please refer to the Table 2 of  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/n2cpu_nii51003.pdf  Kazu