Error compiling sdram.v

[Altera_Forum]

Dear all, 

 I recently created a new project in Verilog to test the Performance counter that seems not working in VHDL projects.  Whereas the verilog fast example distributed with Nios II works fine, the verilog standard and full_fledged examples fail to compile. The behavior is that the nios2 block is generated without problems by SOPC Builder, but when compiled in Quartus it gives the following error:  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  ... Info: Using design file sdram.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project  Info: Found entity 1: sdram_input_efifo_module  Info: Found entity 2: sdram Error: Can&#39;t process assignment. Attribute format is illegal -- parsing error  (line 20). Use legal format for ALTERA_ATTRIBUTE assignment. ... (previous line repeated around 60 times) Error: Can&#39;t elaborate user hierarchy "full_1s40:inst|sdram:the_sdram" Error: Quartus II Analysis & Synthesis was unsuccessful. 65 errors, 244 warnings  Error: Processing ended: Fri Apr 01 10:41:18 2005  Error: Elapsed time: 00:00:40 Error: Quartus II Full Compilation was unsuccessful. 65 errors, 244 warnings[/b]  --- Quote End ---    The error line in sdram.v is something like  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  output [ 31: 0 ] za_data;[/b]  --- Quote End ---    does anyone had the same error before?  Paolo

[Altera_Forum]

Yes, me! 

In the same file! Altera support couldn&#39;t help. You need to open sdram.v with notepad (you will see more than in quartus,..... (!) )  this is the wrong line for my case:   reg     za_data /* synthesis ALTERA_ATTRIBUTE = FAST_INPUT_REGISTER=ON */;  you need to manually add the " :   reg     za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;  ...after every sopc builder generation. Don&#39;t ask why... ciao  Marco